Re: [PATCH 1/2] target/arm: Move initialization of debug ID registers

[Gustavo Romero <gustavo.romero@linaro.org>]

Hi Richard,

On 6/20/24 3:21 PM, Richard Henderson wrote:
> On 6/20/24 11:13, Gustavo Romero wrote:
>> @@ -1268,7 +1268,10 @@ void aarch64_max_tcg_initfn(Object *obj)
>>       t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1);     /* FEAT_SME_FA64 */
>>       cpu->isar.id_aa64smfr0 = t;
>> -    /* Replicate the same data to the 32-bit id registers.  */
>> +    /*
>> +     * Replicate the same values from the 32-bit max CPU to the 32-bit ID
>> +     * registers.
>> +     */
>>       aa32_max_features(cpu);
> 
> I think the previous comment is more accurate.
> 
> There is no separate "32-bit max CPU". There is one "max CPU", which supports both 32-bit and 64-bit modes, and thus has both 32-bit and 64-bit ID registers.
I see. In v2 I reverted to the previous comment. Thanks a lot for the review.


Cheers,
Gustavo

> The rest of the patch looks good.
> 
> 
> r~