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[200.207.104.144]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f9eb3c591bsm14816985ad.165.2024.06.21.07.41.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Jun 2024 07:41:46 -0700 (PDT) Subject: Re: [PATCH 1/2] target/arm: Move initialization of debug ID registers To: Richard Henderson , qemu-devel@nongnu.org, alex.bennee@linaro.org Cc: philmd@linaro.org, peter.maydell@linaro.org References: <20240620181352.3590086-1-gustavo.romero@linaro.org> <20240620181352.3590086-2-gustavo.romero@linaro.org> <2af6449a-f4c2-422c-a92b-cfb11a5ae2d5@linaro.org> From: Gustavo Romero Message-ID: Date: Fri, 21 Jun 2024 11:41:42 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <2af6449a-f4c2-422c-a92b-cfb11a5ae2d5@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=gustavo.romero@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.465, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Richard, On 6/20/24 3:21 PM, Richard Henderson wrote: > On 6/20/24 11:13, Gustavo Romero wrote: >> @@ -1268,7 +1268,10 @@ void aarch64_max_tcg_initfn(Object *obj) >>       t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1);     /* FEAT_SME_FA64 */ >>       cpu->isar.id_aa64smfr0 = t; >> -    /* Replicate the same data to the 32-bit id registers.  */ >> +    /* >> +     * Replicate the same values from the 32-bit max CPU to the 32-bit ID >> +     * registers. >> +     */ >>       aa32_max_features(cpu); > > I think the previous comment is more accurate. > > There is no separate "32-bit max CPU". There is one "max CPU", which supports both 32-bit and 64-bit modes, and thus has both 32-bit and 64-bit ID registers. I see. In v2 I reverted to the previous comment. Thanks a lot for the review. Cheers, Gustavo > The rest of the patch looks good. > > > r~