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From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Bin Meng <bmeng.cn@gmail.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
Date: Tue, 2 Jun 2020 20:28:02 +0800	[thread overview]
Message-ID: <c9f16143-4e9b-a3a8-ffd3-12d43fd2e343@c-sky.com> (raw)
In-Reply-To: <cc1a1671-b926-bb31-1ed2-d2920f0faf38@c-sky.com>

Hi Alistair,

There are still some questions I don't understand.

1. Is the baud rate  or fifo a necessary feature to simulate?
As you can see, qemu_chr_fe_write will send the byte as soon as possible.
When you want to transmit a byte through WDATA,  you can call 
qemu_chr_fe_write directly.

2.  The baud rate calculation method is not strictly right.
I think when a byte write to FIFO,  char_tx_time * 8 is the correct time 
to send the byte instead of
char_tx_time * 4.

3.  Why add a watch here?
> +        s->uart_status |= UART_STATUS_TXEMPTY;
> +        s->uart_intr_state |= INTR_STATE_TX_EMPTY;
> +        s->uart_intr_state &= ~INTR_STATE_TX_WATERMARK;
> +        ibex_uart_update_irqs(s);
> +        return FALSE;
> +    }
> +
> +    ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level);
> +
> +    if (ret >= 0) {
> +        s->tx_level -= ret;
> +        memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level);
> +    }
> +
> +    if (s->tx_level) {
> +        guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
> +                                        ibex_uart_xmit, s);
> +        if (!r) {
> +            s->tx_level = 0;
> +            return FALSE;
> +        }
> +    }
> + 

Zhiwei



  reply	other threads:[~2020-06-02 12:29 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-28 22:14 [PATCH v5 00/11] RISC-V Add the OpenTitan Machine Alistair Francis
2020-05-28 22:14 ` [PATCH v5 01/11] riscv/boot: Add a missing header include Alistair Francis
2020-05-28 22:14 ` [PATCH v5 02/11] target/riscv: Don't overwrite the reset vector Alistair Francis
2020-05-28 22:14 ` [PATCH v5 03/11] target/riscv: Disable the MMU correctly Alistair Francis
2020-06-01  5:24   ` Bin Meng
2020-05-28 22:14 ` [PATCH v5 04/11] target/riscv: Don't set PMP feature in the cpu init Alistair Francis
2020-06-01  5:26   ` Bin Meng
2020-05-28 22:14 ` [PATCH v5 05/11] target/riscv: Add the lowRISC Ibex CPU Alistair Francis
2020-05-28 22:14 ` [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine Alistair Francis
2020-06-09 13:48   ` Damien Hedde
2020-06-09 14:21     ` Philippe Mathieu-Daudé
2020-06-09 23:09       ` Alistair Francis
2020-09-08 14:52   ` Peter Maydell
2020-09-09 17:49     ` Alistair Francis
2020-09-09 19:00       ` Peter Maydell
2020-09-09 19:51         ` Palmer Dabbelt
2020-09-10 18:48           ` Alistair Francis
2023-05-19 17:15   ` [PATCH v5 6/11] " Philippe Mathieu-Daudé
2020-05-28 22:14 ` [PATCH v5 07/11] hw/char: Initial commit of Ibex UART Alistair Francis
2020-06-01 21:23   ` Alistair Francis
2020-06-02 11:22   ` LIU Zhiwei
2020-06-02 12:28     ` LIU Zhiwei [this message]
2020-06-02 17:54       ` Alistair Francis
2020-06-03 10:33         ` LIU Zhiwei
2020-06-03 15:56           ` Alistair Francis
2020-06-04  1:59             ` LIU Zhiwei
2020-06-04  4:35               ` Alistair Francis
2020-06-04  5:05                 ` LIU Zhiwei
2020-06-04  5:46                   ` Alistair Francis
2020-06-04  5:40                 ` LIU Zhiwei
2020-06-02 17:46     ` Alistair Francis
2020-05-28 22:14 ` [PATCH v5 08/11] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
2020-05-28 22:14 ` [PATCH v5 09/11] riscv/opentitan: Connect the PLIC device Alistair Francis
2020-05-28 22:14 ` [PATCH v5 10/11] riscv/opentitan: Connect the UART device Alistair Francis
2020-05-28 22:14 ` [PATCH v5 11/11] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis

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