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From: Gavin Shan <gshan@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Zheyu Ma <zheyuma97@gmail.com>, qemu-stable@nongnu.org
Subject: Re: [PATCH] hw/char/pl011: Use correct masks for IBRD and FBRD
Date: Wed, 9 Oct 2024 16:58:34 +1000	[thread overview]
Message-ID: <ca04ffc9-df13-423d-b864-71e0395ce509@redhat.com> (raw)
In-Reply-To: <20241007144732.2491331-1-peter.maydell@linaro.org>

On 10/8/24 12:47 AM, Peter Maydell wrote:
> In commit b88cfee90268cad we defined masks for the IBRD and FBRD
> integer and fractional baud rate divider registers, to prevent the
> guest from writing invalid values which could cause division-by-zero.
> Unfortunately we got the mask values the wrong way around: the FBRD
> register is six bits and the IBRD register is 16 bits, not
> vice-versa.
> 
> You would only run into this bug if you programmed the UART to a baud
> rate of less than 9600, because for 9600 baud and above the IBRD
> value will fit into 6 bits, as per the table in
>   https://developer.arm.com/documentation/ddi0183/g/programmers-model/register-descriptions/fractional-baud-rate-register--uartfbrd
> 
> The only visible effects would be that the value read back from
> the register by the guest would be truncated, and we would
> print an incorrect baud rate in the debug logs.
> 
> Cc: qemu-stable@nongnu.org
> Fixes: b88cfee90268 ("hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate()")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2610
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   hw/char/pl011.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 

Reviewed-by: Gavin Shan <gshan@redhat.com>



      parent reply	other threads:[~2024-10-09  7:00 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-07 14:47 [PATCH] hw/char/pl011: Use correct masks for IBRD and FBRD Peter Maydell
2024-10-07 17:01 ` Alex Bennée
2024-10-07 19:56 ` Philippe Mathieu-Daudé
2024-10-09  6:58 ` Gavin Shan [this message]

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