[PATCH 0/7] target/i386: add a few simple features

[PATCH 0/7] target/i386: add a few simple features

[Paolo Bonzini]

TCG is not reporting a few features that are actually already implemented,
or that are easy to implement.  Add them.

Paolo

Paolo Bonzini (7):
  target/i386: fix INVD vmexit
  target/i386: TCG supports 3DNow! prefetch(w)
  target/i386: TCG supports RDSEED
  target/i386: TCG supports 32-bit SYSCALL
  target/i386: TCG supports XSAVEERPTR
  target/i386: implement RDPID in TCG
  target/i386: implement WBNOINVD in TCG

 linux-user/i386/target_cpu.h   |  8 ++++++++
 linux-user/x86_64/target_cpu.h |  1 +
 target/i386/cpu.c              | 27 +++++++++++++++++++--------
 target/i386/helper.h           |  2 +-
 target/i386/tcg/misc_helper.c  | 21 +++++++++++++++------
 target/i386/tcg/translate.c    | 33 ++++++++++++++++++++++++++-------
 6 files changed, 70 insertions(+), 22 deletions(-)

-- 
2.40.1

[PATCH 1/7] target/i386: fix INVD vmexit

[Paolo Bonzini]

Due to a typo or perhaps a brain fart, the INVD vmexit was never generated.
Fix it (but not that fixing just the typo would break both INVD and WBINVD,
due to a case of two wrongs making a right).

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/tcg/translate.c | 2 +-
 1 file changed, 1 insertions(+), 1 deletions(-)

diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 5cf14311a60..9783fe80a30 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -6119,7 +6119,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
     case 0x108: /* invd */
     case 0x109: /* wbinvd */
         if (check_cpl0(s)) {
-            gen_svm_check_intercept(s, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
+            gen_svm_check_intercept(s, (b & 1) ? SVM_EXIT_WBINVD : SVM_EXIT_INVD);
             /* nothing to do */
         }
         break;
-- 
2.40.1

Re: [PATCH 1/7] target/i386: fix INVD vmexit

[Richard Henderson]

On 6/18/23 23:51, Paolo Bonzini wrote:
> Due to a typo or perhaps a brain fart, the INVD vmexit was never generated.
> Fix it (but not that fixing just the typo would break both INVD and WBINVD,
> due to a case of two wrongs making a right).
> 
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
>   target/i386/tcg/translate.c | 2 +-
>   1 file changed, 1 insertions(+), 1 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH 2/7] target/i386: TCG supports 3DNow! prefetch(w)

[Paolo Bonzini]

The AMD prefetch(w) instructions have not been deprecated together with the rest
of 3DNow!, and in fact are even supported by newer Intel processor.  Mark them
as supported by TCG, as it supports all of 3DNow!.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/cpu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1242bd541a5..ff3dcd02dcb 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -647,7 +647,8 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
           TCG_EXT2_X86_64_FEATURES)
 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
-          CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
+          CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \
+          CPUID_EXT3_3DNOWPREFETCH)
 #define TCG_EXT4_FEATURES 0
 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \
           CPUID_SVM_SVME_ADDR_CHK)
-- 
2.40.1

Re: [PATCH 2/7] target/i386: TCG supports 3DNow! prefetch(w)

[Richard Henderson]

On 6/18/23 23:51, Paolo Bonzini wrote:
> The AMD prefetch(w) instructions have not been deprecated together with the rest
> of 3DNow!, and in fact are even supported by newer Intel processor.  Mark them
> as supported by TCG, as it supports all of 3DNow!.
> 
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
>   target/i386/cpu.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH 3/7] target/i386: TCG supports RDSEED

[Paolo Bonzini]

TCG implements RDSEED, and in fact uses qcrypto_random_bytes which is
secure enough to match hardware behavior.  Expose it to guests.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/cpu.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ff3dcd02dcb..fc4246223d4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -657,11 +657,10 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
           CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
           CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT |            \
           CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
-          CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2)
+          CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED)
           /* missing:
           CPUID_7_0_EBX_HLE
-          CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
-          CPUID_7_0_EBX_RDSEED */
+          CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */
 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \
           /* CPUID_7_0_ECX_OSPKE is dynamic */ \
           CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES)
-- 
2.40.1

Re: [PATCH 3/7] target/i386: TCG supports RDSEED

[Richard Henderson]

On 6/18/23 23:51, Paolo Bonzini wrote:
> TCG implements RDSEED, and in fact uses qcrypto_random_bytes which is
> secure enough to match hardware behavior.  Expose it to guests.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>   target/i386/cpu.c | 5 ++---
>   1 file changed, 2 insertions(+), 3 deletions(-)

TCG protects both RDRAND and RDSEED with CPUID_EXT_RDRAND.
I guess we should use CPUID_7_0_EBX_RDSEED for RDSEED?


r~

> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index ff3dcd02dcb..fc4246223d4 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -657,11 +657,10 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
>             CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
>             CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT |            \
>             CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
> -          CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2)
> +          CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED)
>             /* missing:
>             CPUID_7_0_EBX_HLE
> -          CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
> -          CPUID_7_0_EBX_RDSEED */
> +          CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */
>   #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \
>             /* CPUID_7_0_ECX_OSPKE is dynamic */ \
>             CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES)

[PATCH 4/7] target/i386: TCG supports 32-bit SYSCALL

[Paolo Bonzini]

TCG supports both 32-bit and 64-bit SYSCALL, so expose it
with "-cpu max" even for 32-bit emulators.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fc4246223d4..be16c66341d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -637,7 +637,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
           CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */
 
 #ifdef TARGET_X86_64
-#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
+#define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM
 #else
 #define TCG_EXT2_X86_64_FEATURES 0
 #endif
@@ -645,7 +645,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
-          TCG_EXT2_X86_64_FEATURES)
+          CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES)
 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \
           CPUID_EXT3_3DNOWPREFETCH)
-- 
2.40.1

Re: [PATCH 4/7] target/i386: TCG supports 32-bit SYSCALL

[Richard Henderson]

On 6/18/23 23:51, Paolo Bonzini wrote:
> TCG supports both 32-bit and 64-bit SYSCALL, so expose it
> with "-cpu max" even for 32-bit emulators.
> 
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
>   target/i386/cpu.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 4/7] target/i386: TCG supports 32-bit SYSCALL

[Paolo Bonzini]

[-- Attachment #1: Type: text/plain, Size: 1933 bytes --]

Il dom 18 giu 2023, 23:51 Paolo Bonzini <pbonzini@redhat.com> ha scritto:

> TCG supports both 32-bit and 64-bit SYSCALL, so expose it
> with "-cpu max" even for 32-bit emulators.
>

Nope, this is broken... My bad for assuming that glibc will use syscall if
available—that doesn't happen because the syscall instruction actually is
in the vsyscall page or vDSO.

The fix is still pretty easy, and even SYSENTER could be supported since
after all QEMU *is* exposing the SEP feature when doing user mode
emulation. SYSENTER's design is so hideous though, that in practice no
program will ever use it outside the vDSO/vsyscall page.

Paolo


> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  target/i386/cpu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index fc4246223d4..be16c66341d 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -637,7 +637,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t
> vendor1,
>            CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */
>
>  #ifdef TARGET_X86_64
> -#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
> +#define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM
>  #else
>  #define TCG_EXT2_X86_64_FEATURES 0
>  #endif
> @@ -645,7 +645,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t
> vendor1,
>  #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
>            CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
>            CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
> -          TCG_EXT2_X86_64_FEATURES)
> +          CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES)
>  #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
>            CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \
>            CPUID_EXT3_3DNOWPREFETCH)
> --
> 2.40.1
>
>

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[PATCH 5/7] target/i386: TCG supports XSAVEERPTR

[Paolo Bonzini]

XSAVEERPTR is actually a fix for an errata; TCG does not have the issue.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/cpu.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index be16c66341d..8e12616db5e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -678,6 +678,8 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
 #define TCG_SGX_12_0_EBX_FEATURES 0
 #define TCG_SGX_12_1_EAX_FEATURES 0
 
+#define TCG_8000_0008_EBX  CPUID_8000_0008_EBX_XSAVEERPTR
+
 FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
     [FEAT_1_EDX] = {
         .type = CPUID_FEATURE_WORD,
@@ -939,7 +941,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
             "amd-psfd", NULL, NULL, NULL,
         },
         .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
-        .tcg_features = 0,
+        .tcg_features = TCG_8000_0008_EBX,
         .unmigratable_flags = 0,
     },
     [FEAT_8000_0021_EAX] = {
-- 
2.40.1

Re: [PATCH 5/7] target/i386: TCG supports XSAVEERPTR

[Richard Henderson]

On 6/18/23 23:51, Paolo Bonzini wrote:
> XSAVEERPTR is actually a fix for an errata; TCG does not have the issue.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>   target/i386/cpu.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[PATCH 6/7] target/i386: implement RDPID in TCG

[Paolo Bonzini]

RDPID corresponds to a RDMSR(TSC_AUX); however, it is unprivileged
so for user-mode emulation we must provide the value that the kernel
places in the MSR.  For Linux, it is a combination of the current CPU
and the current NUMA node, both of which can be retrieved with getcpu(2).
For BSD, just return 0.

RDTSCP is reimplemented as RDTSC + RDPID ECX; the differences in terms
of serializability are not relevant to QEMU.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 linux-user/i386/target_cpu.h   |  8 ++++++++
 linux-user/x86_64/target_cpu.h |  1 +
 target/i386/cpu.c              | 10 +++++++++-
 target/i386/helper.h           |  2 +-
 target/i386/tcg/misc_helper.c  | 21 +++++++++++++++------
 target/i386/tcg/translate.c    | 15 +++++++++++++--
 6 files changed, 47 insertions(+), 10 deletions(-)

diff --git a/linux-user/i386/target_cpu.h b/linux-user/i386/target_cpu.h
index 52caf788cc3..3539f790222 100644
--- a/linux-user/i386/target_cpu.h
+++ b/linux-user/i386/target_cpu.h
@@ -54,4 +54,12 @@ static inline abi_ulong get_sp_from_cpustate(CPUX86State *state)
 {
     return state->regs[R_ESP];
 }
+
+static inline uint32_t get_cpunode(void)
+{
+    unsigned cpu, node;
+    getcpu(&cpu, &node);
+    return (node << 12) | (cpu & 0xfff);
+}
+
 #endif /* I386_TARGET_CPU_H */
diff --git a/linux-user/x86_64/target_cpu.h b/linux-user/x86_64/target_cpu.h
index 9ec7cbb7a4c..dec2e24f5a3 100644
--- a/linux-user/x86_64/target_cpu.h
+++ b/linux-user/x86_64/target_cpu.h
@@ -1 +1,2 @@
+#include "target_syscall.h"
 #include "../i386/target_cpu.h"
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8e12616db5e..68218103108 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -661,9 +661,17 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
           /* missing:
           CPUID_7_0_EBX_HLE
           CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */
+
+#if defined CONFIG_SOFTMMU || defined CONFIG_LINUX
+#define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID
+#else
+#define TCG_7_0_ECX_RDPID 0
+#endif
 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \
           /* CPUID_7_0_ECX_OSPKE is dynamic */ \
-          CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES)
+          CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \
+          TCG_7_0_ECX_RDPID)
+
 #define TCG_7_0_EDX_FEATURES CPUID_7_0_EDX_FSRM
 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \
           CPUID_7_1_EAX_FSRC)
diff --git a/target/i386/helper.h b/target/i386/helper.h
index e627a931073..4e308aae643 100644
--- a/target/i386/helper.h
+++ b/target/i386/helper.h
@@ -69,8 +69,8 @@ DEF_HELPER_2(into, void, env, int)
 DEF_HELPER_FLAGS_1(single_step, TCG_CALL_NO_WG, noreturn, env)
 DEF_HELPER_1(rechecking_single_step, void, env)
 DEF_HELPER_1(cpuid, void, env)
+DEF_HELPER_FLAGS_1(rdpid, TCG_CALL_NO_WG, tl, env)
 DEF_HELPER_1(rdtsc, void, env)
-DEF_HELPER_1(rdtscp, void, env)
 DEF_HELPER_FLAGS_1(rdpmc, TCG_CALL_NO_WG, noreturn, env)
 
 #ifndef CONFIG_USER_ONLY
diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
index 5f7a3061ca5..9bcbf6fd60d 100644
--- a/target/i386/tcg/misc_helper.c
+++ b/target/i386/tcg/misc_helper.c
@@ -24,6 +24,10 @@
 #include "exec/exec-all.h"
 #include "helper-tcg.h"
 
+#if defined CONFIG_USER_ONLY && defined CONFIG_LINUX
+#include "target_cpu.h"
+#endif
+
 /*
  * NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
  * after generating a call to a helper that uses this.
@@ -75,12 +79,6 @@ void helper_rdtsc(CPUX86State *env)
     env->regs[R_EDX] = (uint32_t)(val >> 32);
 }
 
-void helper_rdtscp(CPUX86State *env)
-{
-    helper_rdtsc(env);
-    env->regs[R_ECX] = (uint32_t)(env->tsc_aux);
-}
-
 G_NORETURN void helper_rdpmc(CPUX86State *env)
 {
     if (((env->cr[4] & CR4_PCE_MASK) == 0 ) &&
@@ -137,3 +135,14 @@ void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val)
     env->pkru = val;
     tlb_flush(cs);
 }
+
+target_ulong HELPER(rdpid)(CPUX86State *env)
+{
+#if defined CONFIG_SOFTMMU
+    return env->tsc_aux;
+#elif defined CONFIG_LINUX
+    return get_cpunode();
+#else
+    return 0;
+#endif
+}
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 9783fe80a30..9023f47fa69 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -3924,7 +3924,16 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
             gen_cmpxchg8b(s, env, modrm);
             break;
 
-        case 7: /* RDSEED */
+        case 7: /* RDSEED, RDPID with f3 prefix */
+            if (mod == 3 && !(s->prefix & PREFIX_LOCK) &&
+                (s->prefix & PREFIX_REPZ) &&
+                (s->cpuid_ext_features & CPUID_7_0_ECX_RDPID)) {
+                gen_helper_rdpid(s->T0, cpu_env);
+                rm = (modrm & 7) | REX_B(s);
+                gen_op_mov_reg_v(s, dflag, rm, s->T0);
+                break;
+            }
+            /* fallthrough */
         case 6: /* RDRAND */
             if (mod != 3 ||
                 (s->prefix & (PREFIX_LOCK | PREFIX_REPZ | PREFIX_REPNZ)) ||
@@ -6108,7 +6117,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
             gen_update_cc_op(s);
             gen_update_eip_cur(s);
             translator_io_start(&s->base);
-            gen_helper_rdtscp(cpu_env);
+            gen_helper_rdtsc(cpu_env);
+            gen_helper_rdpid(s->T0, cpu_env);
+            gen_op_mov_reg_v(s, dflag, R_ECX, s->T0);
             break;
 
         default:
-- 
2.40.1

Re: [PATCH 6/7] target/i386: implement RDPID in TCG

[Richard Henderson]

On 6/18/23 23:51, Paolo Bonzini wrote:
> RDPID corresponds to a RDMSR(TSC_AUX); however, it is unprivileged
> so for user-mode emulation we must provide the value that the kernel
> places in the MSR.  For Linux, it is a combination of the current CPU
> and the current NUMA node, both of which can be retrieved with getcpu(2).
> For BSD, just return 0.
> 
> RDTSCP is reimplemented as RDTSC + RDPID ECX; the differences in terms
> of serializability are not relevant to QEMU.
> 
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
>   linux-user/i386/target_cpu.h   |  8 ++++++++
>   linux-user/x86_64/target_cpu.h |  1 +
>   target/i386/cpu.c              | 10 +++++++++-
>   target/i386/helper.h           |  2 +-
>   target/i386/tcg/misc_helper.c  | 21 +++++++++++++++------
>   target/i386/tcg/translate.c    | 15 +++++++++++++--
>   6 files changed, 47 insertions(+), 10 deletions(-)
> 
> diff --git a/linux-user/i386/target_cpu.h b/linux-user/i386/target_cpu.h
> index 52caf788cc3..3539f790222 100644
> --- a/linux-user/i386/target_cpu.h
> +++ b/linux-user/i386/target_cpu.h
> @@ -54,4 +54,12 @@ static inline abi_ulong get_sp_from_cpustate(CPUX86State *state)
>   {
>       return state->regs[R_ESP];
>   }
> +
> +static inline uint32_t get_cpunode(void)
> +{
> +    unsigned cpu, node;
> +    getcpu(&cpu, &node);
> +    return (node << 12) | (cpu & 0xfff);
> +}
> +

What is our minimum glibc version?  This requires 2.29.

Also, not especially fond of the placement.  target/ including linux-user/ header isn't 
nice.  Might as well just place these 3 lines in misc_helper.c to begin.

r~

Re: [PATCH 6/7] target/i386: implement RDPID in TCG

[Paolo Bonzini]

On Mon, Jun 19, 2023 at 9:40 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
> What is our minimum glibc version?  This requires 2.29.

Ok, I'll add a test to meson.build.

> Also, not especially fond of the placement.  target/ including linux-user/ header isn't
> nice.  Might as well just place these 3 lines in misc_helper.c to begin.

Ok. Can be revisited later if BSD needs it, or split between sysemu/
and user/ so that the include is less jarring.

Thanks,

Paolo

[PATCH 7/7] target/i386: implement WBNOINVD in TCG

[Paolo Bonzini]

WBNOINVD is the same as INVD or WBINVD as far as TCG is concerned, but it does
not generate a vmexit if the processor supports it.  If it does not, it is treated
as WBINVD and generates a vmexit.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/cpu.c           |  3 ++-
 target/i386/tcg/translate.c | 10 +++++++++-
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 68218103108..dec376ab56d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -686,7 +686,8 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
 #define TCG_SGX_12_0_EBX_FEATURES 0
 #define TCG_SGX_12_1_EAX_FEATURES 0
 
-#define TCG_8000_0008_EBX  CPUID_8000_0008_EBX_XSAVEERPTR
+#define TCG_8000_0008_EBX  (CPUID_8000_0008_EBX_XSAVEERPTR | \
+          CPUID_8000_0008_EBX_WBNOINVD)
 
 FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
     [FEAT_1_EDX] = {
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 9023f47fa69..c3d4410cdf1 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -122,6 +122,7 @@ typedef struct DisasContext {
     int cpuid_ext3_features;
     int cpuid_7_0_ebx_features;
     int cpuid_7_0_ecx_features;
+    int cpuid_8000_0008_ebx_features;
     int cpuid_xsave_features;
 
     /* TCG local temps */
@@ -6127,8 +6128,14 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
         }
         break;
 
+    case 0x109: /* wbinvd; wbnoinvd with REPZ prefix */
+        if ((s->cpuid_8000_0008_ebx_features & CPUID_8000_0008_EBX_WBNOINVD) &&
+            s->prefix & PREFIX_REPZ) {
+            check_cpl0(s);
+            break;
+        }
+        /* fallthrough */
     case 0x108: /* invd */
-    case 0x109: /* wbinvd */
         if (check_cpl0(s)) {
             gen_svm_check_intercept(s, (b & 1) ? SVM_EXIT_WBINVD : SVM_EXIT_INVD);
             /* nothing to do */
@@ -6936,6 +6943,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
     dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
     dc->cpuid_7_0_ecx_features = env->features[FEAT_7_0_ECX];
     dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
+    dc->cpuid_8000_0008_ebx_features = env->features[FEAT_8000_0008_EBX];
     dc->jmp_opt = !((cflags & CF_NO_GOTO_TB) ||
                     (flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)));
     /*
-- 
2.40.1

Re: [PATCH 7/7] target/i386: implement WBNOINVD in TCG

[Richard Henderson]

On 6/18/23 23:51, Paolo Bonzini wrote:
> WBNOINVD is the same as INVD or WBINVD as far as TCG is concerned, but it does
> not generate a vmexit if the processor supports it.  If it does not, it is treated
> as WBINVD and generates a vmexit.
> 
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
>   target/i386/cpu.c           |  3 ++-
>   target/i386/tcg/translate.c | 10 +++++++++-
>   2 files changed, 11 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~