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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b87632365sm94069375e9.16.2025.09.01.04.05.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Sep 2025 04:05:54 -0700 (PDT) Message-ID: Date: Mon, 1 Sep 2025 13:05:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 01/14] hw/intc: Allow gaps in hartids for aclint and aplic To: Djordje Todorovic , "qemu-devel@nongnu.org" Cc: "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" References: <20250717093833.402237-1-djordje.todorovic@htecgroup.com> <20250717093833.402237-2-djordje.todorovic@htecgroup.com> <5f0fb254-fa9c-4e29-a848-6e9b3bc8274d@linaro.org> <046d60ed-aa62-4357-a812-721de3412573@htecgroup.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <046d60ed-aa62-4357-a812-721de3412573@htecgroup.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/9/25 10:17, Djordje Todorovic wrote: > On 8. 8. 25. 17:52, Philippe Mathieu-Daudé wrote: > >> CAUTION: This email originated from outside of the organization. Do >> not click links or open attachments unless you recognize the sender >> and know the content is safe. >> >> >> On 17/7/25 11:38, Djordje Todorovic wrote: >>> This is needed for riscv based CPUs by MIPS since those may have >>> sparse hart-ID layouts. ACLINT and APLIC still assume a dense >>> range, and if a hart is missing, this causes NULL derefs. >>> >>> Signed-off-by: Chao-ying Fu >>> Signed-off-by: Djordje Todorovic >>> --- >>>   hw/intc/riscv_aclint.c | 21 +++++++++++++++++++-- >>>   hw/intc/riscv_aplic.c  | 11 ++++++++--- >>>   2 files changed, 27 insertions(+), 5 deletions(-) >>> >>> diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c >>> index b0139f03f5..22ac4133d5 100644 >>> --- a/hw/intc/riscv_aclint.c >>> +++ b/hw/intc/riscv_aclint.c >>> @@ -292,7 +292,13 @@ static void >>> riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp) >>>       s->timecmp = g_new0(uint64_t, s->num_harts); >>>       /* Claim timer interrupt bits */ >>>       for (i = 0; i < s->num_harts; i++) { >>> -        RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(s->hartid_base + i)); >>> +        CPUState *cpu_by_hartid = cpu_by_arch_id(s->hartid_base + i); >>> +        if (cpu_by_hartid == NULL) { >>> +            qemu_log_mask(LOG_GUEST_ERROR, "aclint-mtimer: invalid >>> hartid: %u", >>> +                          s->hartid_base + i); >> >> DeviceRealize() handlers are part of machine modelling, not guest uses. >> >> IOW, triggering this is a programming mistake, so we should just >> abort() here. > > Well, if we do it that way, our Boston board target for P8700 cannot run. So the problem is elsewhere :)