qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: Jinjie Ruan <ruanjinjie@huawei.com>,
	peter.maydell@linaro.org, eduardo@habkost.net,
	marcel.apfelbaum@gmail.com, philmd@linaro.org,
	wangyanan55@huawei.com, qemu-devel@nongnu.org,
	qemu-arm@nongnu.org
Subject: Re: [RFC PATCH v3 14/21] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0
Date: Fri, 23 Feb 2024 10:14:02 -1000	[thread overview]
Message-ID: <ca6cd116-8dae-4ddc-95ae-db19e18ae5b5@linaro.org> (raw)
In-Reply-To: <20240223103221.1142518-15-ruanjinjie@huawei.com>

On 2/23/24 00:32, Jinjie Ruan via wrote:
> Add GICR_INMIR0 register and support access GICR_INMIR0.
> 
> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
> ---
>   hw/intc/arm_gicv3_redist.c | 23 +++++++++++++++++++++++
>   hw/intc/gicv3_internal.h   |  1 +
>   2 files changed, 24 insertions(+)
> 
> diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
> index 8153525849..87e7823f34 100644
> --- a/hw/intc/arm_gicv3_redist.c
> +++ b/hw/intc/arm_gicv3_redist.c
> @@ -35,6 +35,15 @@ static int gicr_ns_access(GICv3CPUState *cs, int irq)
>       return extract32(cs->gicr_nsacr, irq * 2, 2);
>   }
>   
> +static void gicr_write_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
> +                                  uint32_t *reg, uint32_t val)
> +{
> +    /* Helper routine to implement writing to a "set" register */
> +    val &= mask_group(cs, attrs);
> +    *reg = val;
> +    gicv3_redist_update(cs);
> +}
> +
>   static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
>                                         uint32_t *reg, uint32_t val)
>   {
> @@ -406,6 +415,13 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset,
>           *data = value;
>           return MEMTX_OK;
>       }
> +    case GICR_INMIR0:
> +        if (!cs->gic->nmi_support) {
> +            *data = 0;
> +            return MEMTX_OK;
> +        }
> +        *data = gicr_read_bitmap_reg(cs, attrs, cs->gicr_isuperprio);
> +        return MEMTX_OK;

Clearer as

     *data = (cs->gic->nmi_support
              ? gicr_read_bitmap_reg(cs, attrs, cs->gicr_isuperprio)
              : 0);
     return MEMTX_OK;

> +    case GICR_INMIR0:
> +        if (!cs->gic->nmi_support) {
> +            return MEMTX_OK;
> +        }
> +        gicr_write_bitmap_reg(cs, attrs, &cs->gicr_isuperprio, value);
> +        return MEMTX_OK;

Likewise,

     if (cs->gic->nmi_support) {
         gicr_write_bitmap_reg(cs, attrs, &cs->gicr_isuperprio, value);
     }
     return MEMTX_OK;


r~


  reply	other threads:[~2024-02-23 20:35 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-23 10:32 [RFC PATCH v3 00/21] target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 01/21] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 02/21] target/arm: Add PSTATE.ALLINT Jinjie Ruan via
2024-02-23 18:39   ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 03/21] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 04/21] target/arm: Implement ALLINT MSR (immediate) Jinjie Ruan via
2024-02-23 19:03   ` Richard Henderson
2024-02-26  2:22     ` Jinjie Ruan via
2024-02-26 19:16       ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 05/21] target/arm: Support MSR access to ALLINT Jinjie Ruan via
2024-02-23 19:08   ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 06/21] target/arm: Add support for Non-maskable Interrupt Jinjie Ruan via
2024-02-23 19:55   ` Richard Henderson
2024-02-26  7:00     ` Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 07/21] target/arm: Add support for NMI in arm_phys_excp_target_el() Jinjie Ruan via
2024-02-23 19:58   ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 08/21] target/arm: Handle IS/FS in ISR_EL1 for NMI Jinjie Ruan via
2024-02-23 20:05   ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 09/21] target/arm: Handle PSTATE.ALLINT on taking an exception Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 10/21] hw/arm/virt: Wire NMI and VNMI irq lines from GIC to CPU Jinjie Ruan via
2024-02-23 20:06   ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 11/21] hw/intc/arm_gicv3: Add external IRQ lines for NMI Jinjie Ruan via
2024-02-23 20:07   ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 12/21] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64() Jinjie Ruan via
2024-02-23 20:07   ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 13/21] hw/intc/arm_gicv3: Add irq superpriority information Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 14/21] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0 Jinjie Ruan via
2024-02-23 20:14   ` Richard Henderson [this message]
2024-02-23 10:32 ` [RFC PATCH v3 15/21] hw/intc/arm_gicv3: Implement GICD_INMIR Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 16/21] hw/intc: Enable FEAT_GICv3_NMI Feature Jinjie Ruan via
2024-02-23 20:14   ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 17/21] hw/intc/arm_gicv3: Add NMI handling CPU interface registers Jinjie Ruan via
2024-02-23 20:52   ` Richard Henderson
2024-02-26 11:22     ` Jinjie Ruan via
2024-02-26 11:32     ` Peter Maydell
2024-02-23 10:32 ` [RFC PATCH v3 18/21] hw/intc/arm_gicv3: Implement NMI interrupt prioirty Jinjie Ruan via
2024-02-23 21:23   ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 19/21] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() Jinjie Ruan via
2024-02-23 21:48   ` Richard Henderson
2024-02-23 10:32 ` [RFC PATCH v3 20/21] target/arm: Add FEAT_NMI to max Jinjie Ruan via
2024-02-23 10:32 ` [RFC PATCH v3 21/21] hw/arm/virt: Add FEAT_GICv3_NMI feature support in virt GIC Jinjie Ruan via
2024-02-23 21:50   ` Richard Henderson
2024-02-23 21:51 ` [RFC PATCH v3 00/21] target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ca6cd116-8dae-4ddc-95ae-db19e18ae5b5@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=eduardo@habkost.net \
    --cc=marcel.apfelbaum@gmail.com \
    --cc=peter.maydell@linaro.org \
    --cc=philmd@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=ruanjinjie@huawei.com \
    --cc=wangyanan55@huawei.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).