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From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>, qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>,
	Jiaxun Yang <jiaxun.yang@flygoat.com>,
	Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
	Aleksandar Rikalo <arikalo@gmail.com>,
	Richard Henderson <richard.henderson@linaro.org>
Subject: Re: [PATCH v3 9/9] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext
Date: Wed, 30 Oct 2024 15:47:42 -0700	[thread overview]
Message-ID: <ca8c111c-7db4-45e2-940a-efc44d600467@linaro.org> (raw)
In-Reply-To: <20241026175349.84523-10-philmd@linaro.org>

On 10/26/24 10:53, Philippe Mathieu-Daudé wrote:
> Loongson fixed-point multiplies and divisions opcodes are
> specific to 64-bit cores (Loongson-2 and Loongson-3 families).
> Simplify by removing the 32-bit checks.
> 
> Reported-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/tcg/loong_translate.c | 41 ++-----------------------------
>   1 file changed, 2 insertions(+), 39 deletions(-)
> 
> diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_translate.c
> index c02e60bb15b..a005c279a3e 100644
> --- a/target/mips/tcg/loong_translate.c
> +++ b/target/mips/tcg/loong_translate.c
> @@ -31,13 +31,6 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt,
>       TCGv t0, t1;
>       TCGLabel *l1, *l2, *l3;
>   
> -    if (is_double) {
> -        if (TARGET_LONG_BITS != 64) {
> -            return false;
> -        }
> -        check_mips_64(s);
> -    }
> -
>       if (rd == 0) {
>           /* Treat as NOP. */
>           return true;
> @@ -61,8 +54,7 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt,
>       tcg_gen_br(l3);
>       gen_set_label(l1);
>   
> -    tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS == 64
> -                                        ? LLONG_MIN : INT_MIN, l2);
> +    tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2);
>       tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
>       tcg_gen_mov_tl(cpu_gpr[rd], t0);
>   
> @@ -93,13 +85,6 @@ static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,
>       TCGv t0, t1;
>       TCGLabel *l1, *l2;
>   
> -    if (is_double) {
> -        if (TARGET_LONG_BITS != 64) {
> -            return false;
> -        }
> -        check_mips_64(s);
> -    }
> -
>       if (rd == 0) {
>           /* Treat as NOP. */
>           return true;
> @@ -147,13 +132,6 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,
>       TCGv t0, t1;
>       TCGLabel *l1, *l2, *l3;
>   
> -    if (is_double) {
> -        if (TARGET_LONG_BITS != 64) {
> -            return false;
> -        }
> -        check_mips_64(s);
> -    }
> -
>       if (rd == 0) {
>           /* Treat as NOP. */
>           return true;
> @@ -173,8 +151,7 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,
>           tcg_gen_ext32u_tl(t1, t1);
>       }
>       tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
> -    tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS == 64
> -                                        ? LLONG_MIN : INT_MIN, l2);
> +    tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2);
>       tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
>       gen_set_label(l1);
>       tcg_gen_movi_tl(cpu_gpr[rd], 0);
> @@ -205,13 +182,6 @@ static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt,
>       TCGv t0, t1;
>       TCGLabel *l1, *l2;
>   
> -    if (is_double) {
> -        if (TARGET_LONG_BITS != 64) {
> -            return false;
> -        }
> -        check_mips_64(s);
> -    }
> -
>       if (rd == 0) {
>           /* Treat as NOP. */
>           return true;
> @@ -257,13 +227,6 @@ static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt,
>   {
>       TCGv t0, t1;
>   
> -    if (is_double) {
> -        if (TARGET_LONG_BITS != 64) {
> -            return false;
> -        }
> -        check_mips_64(s);
> -    }
> -
>       if (rd == 0) {
>           /* Treat as NOP. */
>           return true;

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>

  reply	other threads:[~2024-10-30 22:48 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-26 17:53 [PATCH v3 0/9] target/mips: Convert Loongson LEXT opcodes to decodetree Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 1/9] target/mips: Extract decode_64bit_enabled() helper Philippe Mathieu-Daudé
2024-10-30 22:46   ` Pierrick Bouvier
2024-10-26 17:53 ` [PATCH v3 2/9] target/mips: Simplify Loongson MULTU.G opcode Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 3/9] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 4/9] target/mips: Convert Loongson DDIV.G opcodes to decodetree Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 5/9] target/mips: Convert Loongson DIV.G " Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 6/9] target/mips: Convert Loongson [D]DIVU.G " Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 7/9] target/mips: Convert Loongson [D]MOD[U].G " Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 8/9] target/mips: Convert Loongson [D]MULT[U].G " Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 9/9] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext Philippe Mathieu-Daudé
2024-10-30 22:47   ` Pierrick Bouvier [this message]
2024-10-26 17:55 ` [PATCH v3 0/9] target/mips: Convert Loongson LEXT opcodes to decodetree Philippe Mathieu-Daudé
2024-10-31  3:54 ` Philippe Mathieu-Daudé

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