From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0067DC433F5 for ; Mon, 23 May 2022 16:28:05 +0000 (UTC) Received: from localhost ([::1]:54334 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ntAua-0006l8-Kz for qemu-devel@archiver.kernel.org; Mon, 23 May 2022 12:28:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46878) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ntAtK-0005LQ-2e for qemu-devel@nongnu.org; Mon, 23 May 2022 12:26:46 -0400 Received: from 1.mo548.mail-out.ovh.net ([178.32.121.110]:46829) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ntAtH-0005aj-JS for qemu-devel@nongnu.org; Mon, 23 May 2022 12:26:45 -0400 Received: from mxplan5.mail.ovh.net (unknown [10.109.143.167]) by mo548.mail-out.ovh.net (Postfix) with ESMTPS id DDDA4210B4; Mon, 23 May 2022 16:26:39 +0000 (UTC) Received: from kaod.org (37.59.142.109) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.9; Mon, 23 May 2022 18:26:39 +0200 Authentication-Results: garm.ovh; auth=pass (GARM-109S003a3e4c013-3c71-41fb-bc12-b92795263946, C731B9A3BAA00D555485D2122847869B54396093) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 Message-ID: Date: Mon, 23 May 2022 18:26:38 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [PATCH] pnv/xive2: Don't overwrite PC registers when writing TCTXT registers Content-Language: en-US To: Frederic Barrat , , , References: <20220523151859.72283-1-fbarrat@linux.ibm.com> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= In-Reply-To: <20220523151859.72283-1-fbarrat@linux.ibm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [37.59.142.109] X-ClientProxiedBy: DAG6EX1.mxp5.local (172.16.2.51) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: 13d22c9c-b6b6-4b57-8f6a-540f1e57d782 X-Ovh-Tracer-Id: 13096186243207039968 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvfedrjedugdejtdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefkffggfgfuvfhfhfgjtgfgihesthekredttdefjeenucfhrhhomhepveorughrihgtpgfnvggpifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpeeigedvffekgeeftedutddttdevudeihfegudffkeeitdekkeetkefhffelveelleenucfkpheptddrtddrtddrtddpfeejrdehledrudegvddruddtleenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdpnhgspghrtghpthhtohepuddprhgtphhtthhopehqvghmuhdquggvvhgvlhesnhhonhhgnhhurdhorhhg Received-SPF: pass client-ip=178.32.121.110; envelope-from=clg@kaod.org; helo=1.mo548.mail-out.ovh.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/23/22 17:18, Frederic Barrat wrote: > When writing a register from the TCTXT memory region (4th page within > the IC BAR), we were overwriting the Presentation Controller (PC) > register at the same offset. It looks like a silly cut and paste > error. Very silly indeed :) > We were somehow lucky: the TCTXT registers being touched are > TCTXT_ENx/_SET/_RESET to enable physical threads and the PC registers > at the same offset are either not used by our model or the update was > harmless. > > Found through code inspection. > > Signed-off-by: Frederic Barrat Reviewed-by: Cédric Le Goater Thanks, C. > --- > hw/intc/pnv_xive2.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c > index 87303b4064..a39e070e82 100644 > --- a/hw/intc/pnv_xive2.c > +++ b/hw/intc/pnv_xive2.c > @@ -1295,7 +1295,6 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, > uint64_t val, unsigned size) > { > PnvXive2 *xive = PNV_XIVE2(opaque); > - uint32_t reg = offset >> 3; > > switch (offset) { > /* > @@ -1322,8 +1321,6 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, > xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset); > return; > } > - > - xive->pc_regs[reg] = val; > } > > static const MemoryRegionOps pnv_xive2_ic_tctxt_ops = {