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[174.92.28.28]) by smtp.gmail.com with ESMTPSA id c73sm13041373qkg.6.2021.03.22.21.17.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Mar 2021 21:17:27 -0700 (PDT) Message-ID: Subject: Re: [PATCH 1/2] hw/intc: GICv3 ITS implementation From: shashi.mallela@linaro.org To: Peter Maydell Date: Tue, 23 Mar 2021 00:17:26 -0400 In-Reply-To: References: <20210315164931.23477-1-shashi.mallela@linaro.org> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-14.el8) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::830; envelope-from=shashi.mallela@linaro.org; helo=mail-qt1-x830.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Leif Lindholm , QEMU Developers , qemu-arm , Radoslaw Biernacki Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Peter, As per your suggestion, i have split the series into smaller pieces and shared newer patch-sets for review including cover letter. Also,have added virt board support and tested the same for functionality using kvm-unit-tests. Please ignore this patch and consider the latest series patchset for review. Thanks Shashi On Tue, 2021-03-16 at 16:15 +0000, Peter Maydell wrote: > On Mon, 15 Mar 2021 at 16:49, Shashi Mallela < > shashi.mallela@linaro.org> wrote: > > Implementation of Interrupt Translation Service which allows > > eventid > > from devices to be translated to physical LPI IntIds.Extended the > > redistributor functionality to process LPI Interrupts as well. > > > > Signed-off-by: Shashi Mallela > > --- > > hw/intc/arm_gicv3.c | 6 + > > hw/intc/arm_gicv3_common.c | 20 +- > > hw/intc/arm_gicv3_cpuif.c | 15 +- > > hw/intc/arm_gicv3_dist.c | 22 +- > > hw/intc/arm_gicv3_its.c | 1386 > > ++++++++++++++++++++++++ > > hw/intc/arm_gicv3_its_common.c | 17 +- > > hw/intc/arm_gicv3_its_kvm.c | 2 +- > > hw/intc/arm_gicv3_redist.c | 163 ++- > > hw/intc/gicv3_internal.h | 169 ++- > > hw/intc/meson.build | 1 + > > include/hw/intc/arm_gicv3_common.h | 13 + > > include/hw/intc/arm_gicv3_its_common.h | 12 +- > > 12 files changed, 1807 insertions(+), 19 deletions(-) > > create mode 100644 hw/intc/arm_gicv3_its.c > > Hi; thanks for posting this. Unfortuantely 1800 lines is much > too large a patch to be reviewable. Could you split the series > up into smaller pieces, please? One possible structure would be > to have a patch with the framework of the device but no actual > implementation of register behaviour or command handling, > followed by patches which add the behaviour piece by piece, > and then finally the patch adding it to the board. > > I think it would also be useful to have the virt board > support, as a demonstration that the emulated ITS and > the KVM ITS have the same interface to the board code > and are basically drop-in-replacements. > > Finally, for multi-patch series, please always send a cover letter > (the "0/5" email, which the other patch emails are followups to; > git format-patch should do this for you). > > thanks > -- PMM