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Content-Language: en-US To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , npiggin@gmail.com, qemu-ppc@nongnu.org Cc: danielhb413@gmail.com, david@gibson.dropbear.id.au, qemu-devel@nongnu.org References: <20231122092845.973949-1-harshpb@linux.ibm.com> <20231122092845.973949-2-harshpb@linux.ibm.com> From: Harsh Prateek Bora In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: lavIby-nI-ZOgwUHcCgtjZ9OMJX2Nwb7 X-Proofpoint-ORIG-GUID: ZhrQOBWTbMeC5cKA9zw0n0hPLv3xVRRw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-23_02,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 suspectscore=0 clxscore=1015 spamscore=0 malwarescore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311230034 Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -36 X-Spam_score: -3.7 X-Spam_bar: --- X-Spam_report: (-3.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.672, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/22/23 17:01, Cédric Le Goater wrote: > Hello Harsh, > > Please add to your .git/config file: > > [diff] >     orderFile = /path/to/qemu/scripts/git.orderfile > Sure, thanks for the suggestion. > > On 11/22/23 10:28, Harsh Prateek Bora wrote: >> spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE to refer to >> the range of CPU IPIs during initialization of nr-irqs property. >> It is more appropriate to have its own define which can be further >> reused as appropriate for correct interpretation. >> >> Signed-off-by: Harsh Prateek Bora >> Suggested-by: Cedric Le Goater >> --- >>   hw/ppc/spapr_irq.c         | 4 ++-- >>   include/hw/ppc/spapr_irq.h | 1 + >>   2 files changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c >> index a0d1e1298e..0c5db6b161 100644 >> --- a/hw/ppc/spapr_irq.c >> +++ b/hw/ppc/spapr_irq.c >> @@ -329,7 +329,7 @@ void spapr_irq_init(SpaprMachineState *spapr, >> Error **errp) >>           int i; >>           dev = qdev_new(TYPE_SPAPR_XIVE); >> -        qdev_prop_set_uint32(dev, "nr-irqs", smc->nr_xirqs + >> SPAPR_XIRQ_BASE); >> +        qdev_prop_set_uint32(dev, "nr-irqs", smc->nr_xirqs + >> SPAPR_NR_IPIS); > > SPAPR_IRQ_NR_IPIS ? > >>           /* >>            * 8 XIVE END structures per CPU. One for each available >>            * priority >> @@ -356,7 +356,7 @@ void spapr_irq_init(SpaprMachineState *spapr, >> Error **errp) >>       } >>       spapr->qirqs = qemu_allocate_irqs(spapr_set_irq, spapr, >> -                                      smc->nr_xirqs + SPAPR_XIRQ_BASE); >> +                                      smc->nr_xirqs + SPAPR_NR_IPIS); >>       /* >>        * Mostly we don't actually need this until reset, except that not >> diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h >> index c22a72c9e2..e7a80a8349 100644 >> --- a/include/hw/ppc/spapr_irq.h >> +++ b/include/hw/ppc/spapr_irq.h >> @@ -28,6 +28,7 @@ > > In include/hw/ppc/spapr_irq.h, we should describe the ranges a bit more. > See commit dcc345b61ebe and ad8de98636e7 for more info. Something like : > >   /* >    * The XIVE IRQ backend uses the same layout as the XICS backend but >    * covers the full range of the IRQ number space. The IRQ numbers for >    * the CPU IPIs are allocated at the bottom of this space, below 4K, >    * to preserve compatibility with XICS which does not use that range. >    */ > >   /* >    * CPU IPI range (XIVE only) >    */ >   #define SPAPR_IRQ_IPI        0x0 >   #define SPAPR_IRQ_NR_IPIS    0x1000 > >   /* >    * IRQ range offsets per device type >    */ >   #define SPAPR_XIRQ_BASE      XICS_IRQ_BASE /* 0x1000 */ > > > And to make sure the ranges don't overlap, let's add : > >   QEMU_BUILD_BUG_ON(SPAPR_IRQ_NR_IPIS > SPAPR_XIRQ_BASE) > Yeh, this looks much better. Will update and post. regards, Harsh > > Thanks, > > C. > >