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Thu, 15 May 2025 16:17:09 +0000 (GMT) Message-ID: Subject: Re: [PATCH 50/50] ppc/xive2: Enable lower level contexts on VP push From: Miles Glenn To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, =?ISO-8859-1?Q?Fr=E9d=E9ric?= Barrat , Michael Kowal , Caleb Schlossin Date: Thu, 15 May 2025 11:17:09 -0500 In-Reply-To: <20250512031100.439842-51-npiggin@gmail.com> References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-51-npiggin@gmail.com> Organization: IBM Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-27.el8_10) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=IqAecK/g c=1 sm=1 tr=0 ts=68261388 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VnNF1IyMAAAA:8 a=pGLkceISAAAA:8 a=z2KaQxLorgeo9JcVKagA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: ZMBZDkl-ehPzHFjpnsvTBVsXWipZvnNF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE2MCBTYWx0ZWRfX973ewl4M2u1y Q5JsXtAcKE/njqIyicPS3zGBS+lTpaMnNE/K+3V0169Oc+x7R1KXRT4JVIhq306Li9cMvArC2EY vGMaEXNwLKCqVZFBJQEQYBlj4odb+EWYfKO2Z7gvJ1Y40K/5UAvNUPRyAHnOHKMyQls1TWshWFN 3+Ivh32Z05dAykd9WuV9zEdELdg+Syk/xciUkIiR0vIflKB4s6R+b3uJIq9bwDX4DcXdJAzhiyN RMhRsBPmp7T2aE/tRre3Cs3JGOhU6iPfIQhiXZryv1dyqeNWrZei8CreC7oR5cuHyVoFt5w3cHP LDZQBCdlm85l7D0Ilr+uzOdqSRHzamOhjA3E8tJd3444e0eaI2rDqu3de19S2CrXnCs/tcljgFB fsG3rCBm7NyXa5esEsCNuIZhMxpnuiztFQr2/V6KSwvSteTFwfhWEXEd/m/z9oamfDSF9KnH X-Proofpoint-GUID: E83uob2WaNsjur1HLduXn81prnZly2i6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_07,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 spamscore=0 mlxlogscore=793 bulkscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150160 Received-SPF: pass client-ip=148.163.158.5; envelope-from=milesg@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Glenn Miles On Mon, 2025-05-12 at 13:10 +1000, Nicholas Piggin wrote: > When pushing a context, the lower-level context becomes valid if it > had V=1, and so on. Iterate lower level contexts and send them > pending interrupts if they become enabled. > > Signed-off-by: Nicholas Piggin > --- > hw/intc/xive2.c | 36 ++++++++++++++++++++++++++++-------- > 1 file changed, 28 insertions(+), 8 deletions(-) > > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index 53e90b8178..ded003fa87 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -995,6 +995,12 @@ static void xive2_tm_push_ctx(XivePresenter *xptr, XiveTCTX *tctx, > bool v; > bool do_restore; > > + if (xive_ring_valid(tctx, ring)) { > + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Attempt to push VP to enabled" > + " ring 0x%02x\n", ring); > + return; > + } > + > /* First update the thead context */ > switch (size) { > case 1: > @@ -1021,19 +1027,32 @@ static void xive2_tm_push_ctx(XivePresenter *xptr, XiveTCTX *tctx, > /* Check the interrupt pending bits */ > if (v) { > Xive2Router *xrtr = XIVE2_ROUTER(xptr); > - uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); > - uint8_t nsr = sig_regs[TM_NSR]; > + uint8_t cur_ring; > > xive2_tctx_restore_nvp(xrtr, tctx, ring, > nvp_blk, nvp_idx, do_restore); > > - if (xive_nsr_indicates_group_exception(ring, nsr)) { > - /* redistribute precluded active grp interrupt */ > - g_assert(ring == TM_QW2_HV_POOL); /* PHYS ring has the interrupt */ > - xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, nsr)); > + for (cur_ring = TM_QW1_OS; cur_ring <= ring; > + cur_ring += XIVE_TM_RING_SIZE) { > + uint8_t *sig_regs = xive_tctx_signal_regs(tctx, cur_ring); > + uint8_t nsr = sig_regs[TM_NSR]; > + > + if (!xive_ring_valid(tctx, cur_ring)) { > + continue; > + } > + > + if (cur_ring == TM_QW2_HV_POOL) { > + if (xive_nsr_indicates_exception(cur_ring, nsr)) { > + g_assert(xive_nsr_exception_ring(cur_ring, nsr) == > + TM_QW3_HV_PHYS); > + xive2_redistribute(xrtr, tctx, > + xive_nsr_exception_ring(ring, nsr)); > + } > + xive2_tctx_process_pending(tctx, TM_QW3_HV_PHYS); > + break; > + } > + xive2_tctx_process_pending(tctx, cur_ring); > } > - xive2_tctx_process_pending(tctx, ring == TM_QW2_HV_POOL ? > - TM_QW3_HV_PHYS : ring); > } > } > > @@ -1159,6 +1178,7 @@ static void xive2_tctx_process_pending(XiveTCTX *tctx, uint8_t sig_ring) > int rc; > > g_assert(sig_ring == TM_QW3_HV_PHYS || sig_ring == TM_QW1_OS); > + g_assert(sig_regs[TM_WORD2] & 0x80); > g_assert(!xive_nsr_indicates_group_exception(sig_ring, sig_regs[TM_NSR])); > > /*