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Tue, 03 Dec 2024 01:59:26 -0800 (PST) Received: from [192.168.69.223] ([176.187.209.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385e0d4778dsm11412369f8f.45.2024.12.03.01.59.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Dec 2024 01:59:26 -0800 (PST) Message-ID: Date: Tue, 3 Dec 2024 10:59:24 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] binfmt: Don't consider riscv{32,64} part of the same family To: Andrea Bolognani , qemu-devel@nongnu.org, qemu-riscv Cc: Laurent Vivier , David Abdurachmanov , =?UTF-8?Q?Daniel_P_=2E_Berrang=C3=A9?= , Richard Henderson , Mark Corbin References: <20241203094702.124748-1-abologna@redhat.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20241203094702.124748-1-abologna@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Andrea, On 3/12/24 10:47, Andrea Bolognani wrote: > Currently the script won't generate a configuration file that > sets up qemu-user-riscv32 on riscv64, likely under the > assumption that 64-bit RISC-V machines can natively run 32-bit I'm confused by the "machines" description used for user emulation. > RISC-V code. > > However this functionality, while theoretically possible, in > practice is missing from most commonly available RISC-V hardware > and not enabled at the distro level. So qemu-user-riscv32 really > is the only option to run riscv32 binaries on riscv64. We have definitions such ELF_ARCH/ELF_PLATFORM/ELF_MACHINE to parse ELF header and select the best CPU / flags. Maybe RISC-V lacks them? BTW we should expose that for linux-user as target_arch_elf.h, like bsd-user does, that would reduce all these #ifdef'ry in linux-user/elfload.c... > > Make riscv32 and riscv64 each its own family, so that the > configuration file we need to make 32-on-64 userspace emulation > work gets generated. Does this patch aim for 9.2? Otherwise FYI I'm working on unifying 32/64-bit targets, maybe for 10.0... > > Link: https://src.fedoraproject.org/rpms/qemu/pull-request/72 > Thanks: David Abdurachmanov > Thanks: Daniel P. Berrangé > Signed-off-by: Andrea Bolognani > --- > scripts/qemu-binfmt-conf.sh | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) > > diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh > index 6ef9f118d9..e38b767c24 100755 > --- a/scripts/qemu-binfmt-conf.sh > +++ b/scripts/qemu-binfmt-conf.sh > @@ -110,11 +110,11 @@ hppa_family=hppa > > riscv32_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xf3\x00' > riscv32_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' > -riscv32_family=riscv > +riscv32_family=riscv32 > > riscv64_magic='\x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xf3\x00' > riscv64_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' > -riscv64_family=riscv > +riscv64_family=riscv64 > > xtensa_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x5e\x00' > xtensa_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' > @@ -168,9 +168,6 @@ qemu_get_family() { > sparc*) > echo "sparc" > ;; > - riscv*) > - echo "riscv" > - ;; > loongarch*) > echo "loongarch" > ;;