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[213.30.8.110]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f58ec8f1sm16629888f8f.26.2025.05.13.10.12.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 May 2025 10:12:16 -0700 (PDT) Message-ID: Date: Tue, 13 May 2025 18:12:15 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 30/48] target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptw To: Richard Henderson , Pierrick Bouvier , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, alex.bennee@linaro.org, anjo@rev.ng, qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini References: <20250512180502.2395029-1-pierrick.bouvier@linaro.org> <20250512180502.2395029-31-pierrick.bouvier@linaro.org> <91cd9b9a-8c67-47d3-8b19-ebaf0b4fab5d@linaro.org> <39c6f5ab-6e45-491d-a0e8-07408e29e2f8@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <39c6f5ab-6e45-491d-a0e8-07408e29e2f8@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 13/5/25 19:03, Richard Henderson wrote: > On 5/13/25 03:41, Philippe Mathieu-Daudé wrote: >> On 12/5/25 20:04, Pierrick Bouvier wrote: >>> This function needs 64 bit compare exchange, so we hide implementation >>> for hosts not supporting it (some 32 bit target, which don't run 64 bit >>> guests anyway). >>> >>> Reviewed-by: Richard Henderson >>> Signed-off-by: Pierrick Bouvier >>> --- >>>   target/arm/ptw.c | 2 +- >>>   1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/target/arm/ptw.c b/target/arm/ptw.c >>> index 68ec3f5e755..44170d831cc 100644 >>> --- a/target/arm/ptw.c >>> +++ b/target/arm/ptw.c >>> @@ -737,7 +737,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, >>> uint64_t old_val, >>>                                uint64_t new_val, S1Translate *ptw, >>>                                ARMMMUFaultInfo *fi) >>>   { >>> -#if defined(TARGET_AARCH64) && defined(CONFIG_TCG) >>> +#if defined(CONFIG_ATOMIC64) && defined(CONFIG_TCG) >>>       uint64_t cur_val; >>>       void *host = ptw->out_host; >> >> I'd feel safer squashing: >> >> -- >8 -- >> @@ -743,2 +743,5 @@ static uint64_t arm_casq_ptw(CPUARMState *env, >> uint64_t old_val, >> >> +    /* AArch32 does not have FEAT_HADFS */ >> +    assert(cpu_isar_feature(aa64_hafs, env_archcpu(env))); > > Why?  This is checked in the setting of param.{ha,hd}. > See aa{32,64}_va_parameters. I suppose the "AArch32 does not have FEAT_HADFS" is misleading then. Better if no changes are necessary and this series can go as is.