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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-451f9924a6esm18909195e9.38.2025.06.05.03.02.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Jun 2025 03:02:05 -0700 (PDT) Message-ID: Date: Thu, 5 Jun 2025 12:02:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root Complex association Content-Language: en-US To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, linuxarm@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org References: <20250602154110.48392-1-shameerali.kolothum.thodi@huawei.com> <20250602154110.48392-2-shameerali.kolothum.thodi@huawei.com> <15b1fd04-2dd0-4191-8958-9d8db8dff7c9@redhat.com> In-Reply-To: <15b1fd04-2dd0-4191-8958-9d8db8dff7c9@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.128, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: eric.auger@redhat.com X-ACL-Warn: , Eric Auger From: Eric Auger via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/5/25 11:53 AM, Eric Auger wrote: > > > On 6/2/25 5:41 PM, Shameer Kolothum wrote: >> Although this change does not affect functionality at present, it is >> required when we add support for user-creatable SMMUv3 devices in >> future patches. >> >> Signed-off-by: Shameer Kolothum >> --- >> hw/arm/smmuv3.c | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c >> index ab67972353..7e934336c2 100644 >> --- a/hw/arm/smmuv3.c >> +++ b/hw/arm/smmuv3.c >> @@ -24,6 +24,7 @@ >> #include "hw/qdev-properties.h" >> #include "hw/qdev-core.h" >> #include "hw/pci/pci.h" >> +#include "hw/pci/pci_bridge.h" >> #include "cpu.h" >> #include "exec/target_page.h" >> #include "trace.h" >> @@ -1881,6 +1882,13 @@ static void smmu_realize(DeviceState *d, Error **errp) >> SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s); >> SysBusDevice *dev = SYS_BUS_DEVICE(d); >> Error *local_err = NULL; >> + Object *bus; >> + >> + bus = object_property_get_link(OBJECT(d), "primary-bus", &error_abort); >> + if (!bus || !object_dynamic_cast(bus->parent, TYPE_PCI_HOST_BRIDGE)) { >> + error_setg(errp, "SMMUv3 is not attached to any PCIe Root Complex!"); >> + return; >> + } > shouldn't you check as well that !pci_bus_bypass_iommu(bus)? I see you do the check in 6/6 and I think this is the correct way because in case of legacy SMMU it is allowed to have pci_bus_bypass_iommu set on the root bus to let the SMMU apply only on pxb buses only. So please ignore this comment. Eric > > Eric >> >> c->parent_realize(d, &local_err); >> if (local_err) { >