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[83.11.37.15]) by smtp.gmail.com with ESMTPSA id l9-20020a17090615c900b00a555be38aaasm16473140ejd.164.2024.05.01.11.08.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 May 2024 11:08:07 -0700 (PDT) Message-ID: Date: Wed, 1 May 2024 20:08:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT To: Richard Henderson , Peter Maydell Cc: Dorjoy Chowdhury , qemu-devel@nongnu.org, Leif Lindholm References: <20240419183135.12276-1-dorjoychy111@gmail.com> <753b3a55-9589-4dcb-b656-8b3025e847df@linaro.org> From: Marcin Juszkiewicz Content-Language: pl-PL, en-GB, en-HK Organization: Linaro In-Reply-To: <753b3a55-9589-4dcb-b656-8b3025e847df@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=marcin.juszkiewicz@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org W dniu 22.04.2024 o 17:21, Richard Henderson pisze: >>> For Arm's CPUs they fall into two categories: >>>   * older ones don't set MT in their MPIDR, and the Aff0 >>>     field is effectively the CPU number >>>   * newer ones do set MT in their MPIDR, but don't have >>>     SMT, so their Aff0 is always 0 and their Aff1 >>>     is the CPU number >>> >>> Of all the CPUs we model, none of them are the >>> architecturally-permitted "MT is set, CPU implements >>> actual SMT, Aff0 indicates the thread in the CPU" type. >> >> Looking at the TRM, Neoverse-E1 is "MT is set, actual SMT, >> Aff0 is the thread" (Aff0 can be 0 or 1). We just don't >> model that CPU type yet. But we should probably make >> sure we don't block ourselves into a corner where that >> would be awkward -- I'll have a think about this and >> look at what x86 does with the topology info. > > I'm suggesting that we set things up per -smp, and if the user chooses a > -cpu value for which that topology doesn't make sense, we do it anyway > and let them keep both pieces. Aff[0-3] are 8 bit each. On those cpus where they exist. So "-smp 512" (maximum allowed for sbsa-ref) would need to be split to 2 clusters by 256 cores or 64 clusters of 8 cores each like it is today so it is backward compatible with whatever assumption firmware/OS does. But if we go for 'newer, better MPIDR_EL1' then maybe it is time to set U bit [30] if "-smp X,sockets=Y" where Y > 1? Or when NUMA config with multiple cpu nodes are setup. Also a way to know which AffX fields to check on firmware/OS side would be nice. A57/72 use Aff[1-2], N1+ use Aff[0-3]. Sure, it can be checked by going through cores, reading then MPIDR_EL1 and if 7:0 has same value on all of them then check Aff[1-3], otherwise Aff[1-2].