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Fri, 12 Aug 2022 14:40:29 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7EB0C4C04A; Fri, 12 Aug 2022 14:40:29 +0000 (GMT) Received: from [9.101.4.17] (unknown [9.101.4.17]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 12 Aug 2022 14:40:29 +0000 (GMT) Message-ID: Date: Fri, 12 Aug 2022 16:40:29 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH for-7.2 v4 03/11] ppc/pnv: set root port chassis and slot using Bus properties Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, clg@kaod.org References: <20220811163950.578927-1-danielhb413@gmail.com> <20220811163950.578927-4-danielhb413@gmail.com> From: Frederic Barrat In-Reply-To: <20220811163950.578927-4-danielhb413@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: wSUNiGOZNgoOkAUWWOra9p4-eb2-1A2T X-Proofpoint-ORIG-GUID: EhRwkBmJqBHIz-XK6ZEDwQokvnZNjohc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-12_09,2022-08-11_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 priorityscore=1501 malwarescore=0 adultscore=0 clxscore=1015 spamscore=0 mlxscore=0 mlxlogscore=999 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208120040 Received-SPF: pass client-ip=148.163.158.5; envelope-from=fbarrat@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/08/2022 18:39, Daniel Henrique Barboza wrote: > For default root ports we have a way of accessing chassis and slot, > before root_port_realize(), via pnv_phb_attach_root_port(). For the > future user created root ports this won't be the case: we can't use > this helper because we don't have access to the PHB phb-id/chip-id > values. > > In earlier patches we've added phb-id and chip-id to pnv-phb-root-bus > objects. We're now able to use the bus to retrieve them. The bus is > reachable for both user created and default devices, so we're changing > all the code paths. This also allow us to validate these changes with > the existing default devices. > > Reviewed-by: Cédric Le Goater > Signed-off-by: Daniel Henrique Barboza > --- Reviewed-by: Frederic Barrat Fred > hw/pci-host/pnv_phb.c | 25 ++++++++++++++++--------- > 1 file changed, 16 insertions(+), 9 deletions(-) > > diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c > index c47ed92462..826c0c144e 100644 > --- a/hw/pci-host/pnv_phb.c > +++ b/hw/pci-host/pnv_phb.c > @@ -25,21 +25,19 @@ > * QOM id. 'chip_id' is going to be used as PCIE chassis for the > * root port. > */ > -static void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id) > +static void pnv_phb_attach_root_port(PCIHostState *pci) > { > PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT); > - g_autofree char *default_id = g_strdup_printf("%s[%d]", > - TYPE_PNV_PHB_ROOT_PORT, > - index); > const char *dev_id = DEVICE(root)->id; > + g_autofree char *default_id = NULL; > + int index; > + > + index = object_property_get_int(OBJECT(pci->bus), "phb-id", &error_fatal); > + default_id = g_strdup_printf("%s[%d]", TYPE_PNV_PHB_ROOT_PORT, index); > > object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id, > OBJECT(root)); > > - /* Set unique chassis/slot values for the root port */ > - qdev_prop_set_uint8(DEVICE(root), "chassis", chip_id); > - qdev_prop_set_uint16(DEVICE(root), "slot", index); > - > pci_realize_and_unref(root, pci->bus, &error_fatal); > } > > @@ -93,7 +91,7 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp) > pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend)); > } > > - pnv_phb_attach_root_port(pci, phb->phb_id, phb->chip_id); > + pnv_phb_attach_root_port(pci); > } > > static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge, > @@ -162,9 +160,18 @@ static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp) > { > PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); > PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev); > + PCIBus *bus = PCI_BUS(qdev_get_parent_bus(dev)); > PCIDevice *pci = PCI_DEVICE(dev); > uint16_t device_id = 0; > Error *local_err = NULL; > + int chip_id, index; > + > + chip_id = object_property_get_int(OBJECT(bus), "chip-id", &error_fatal); > + index = object_property_get_int(OBJECT(bus), "phb-id", &error_fatal); > + > + /* Set unique chassis/slot values for the root port */ > + qdev_prop_set_uint8(dev, "chassis", chip_id); > + qdev_prop_set_uint16(dev, "slot", index); > > rpc->parent_realize(dev, &local_err); > if (local_err) {