From: Richard Henderson <richard.henderson@linaro.org>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
qemu-devel@nongnu.org
Cc: david.brenken@efs-auto.de, georg.hofstetter@efs-auto.de,
andreas.konopik@efs-auto.de
Subject: Re: [PATCH 1/2] target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2
Date: Sat, 6 Mar 2021 23:34:34 -0800 [thread overview]
Message-ID: <cb6e7c44-0472-a545-ea9e-b28e446168c9@linaro.org> (raw)
In-Reply-To: <20210305132629.755627-2-kbastian@mail.uni-paderborn.de>
On 3/5/21 5:26 AM, Bastian Koppelmann wrote:
> @@ -6989,6 +6989,7 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
> uint32_t op2;
> int r1, r2, r3;
> int32_t pos, width;
> + TCGv temp;
>
> op2 = MASK_OP_RRPW_OP2(ctx->opcode);
> r1 = MASK_OP_RRPW_S1(ctx->opcode);
> @@ -7021,10 +7022,15 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
> break;
> case OPC2_32_RRPW_IMASK:
> CHECK_REG_PAIR(r3);
> + temp = tcg_temp_new();
> +
> if (pos + width <= 32) {
> - tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos);
> + tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos);
> tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
> + tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp);
> }
> +
> + tcg_temp_free(temp);
You could restrict the variable to the if block.
Either way,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-03-07 7:36 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-05 13:26 [PATCH 0/2] tricore: IMASK/EXTR corner case fixes Bastian Koppelmann
2021-03-05 13:26 ` [PATCH 1/2] target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2 Bastian Koppelmann
2021-03-07 7:34 ` Richard Henderson [this message]
2021-03-05 13:26 ` [PATCH 2/2] target/tricore: Fix OPC2_32_RRPW_EXTR for width=0 Bastian Koppelmann
2021-03-05 13:31 ` Philippe Mathieu-Daudé
2021-03-07 7:36 ` Richard Henderson
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