From: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: "QEMU devel" <qemu-devel@nongnu.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: Re: [PATCH] mips64el-softmmu: Enable MTTCG
Date: Wed, 05 Jun 2024 13:47:10 +0100 [thread overview]
Message-ID: <cbc243e6-b77e-4f52-88c5-04b94dad1d20@app.fastmail.com> (raw)
In-Reply-To: <87h6e8g9p3.fsf@draig.linaro.org>
在2024年6月4日六月 下午1:43,Alex Bennée写道:
[...]
>
> I'm a little uncomfortable about making the success of MTTCG depend on
> the user options passed to the kernel.
Yes, I agree, it sounds awkward.
>
> How come a non-icount run depends on how many instructions are being run
> on each core? Why is time not based on the wallclock time and by
> definition synced between all cores?
That's the problem of Guest Kernel, the synchronisation mechanism is poorly
written that relies on instruction latency too much. I have patch pending to
improve it at guest side, but we can't fix it in existing binary.
This clock, CP0_Counter, as per ISA spec, is independent between cores and
needs to be synchronized by software. We can emulate it as a monotonic clock
source and Linux should be happy with it, but that is violating ISA spec.
>
>> In non-MTTCG build, the execution is slow enough so kernel won't
>> observe back drifts.
>>
>> Test results:
>>
>> With clocksource=MIPS
>> ```
>> ~/tmp/retry/retry.py -n 100 -c -- ./qemu-system-mips64el \
>> -display none -vga none -serial mon:stdio \
>> -machine malta -kernel ./vmlinux-4.7.0-rc1.I6400 \
>> -cpu I6400 -smp 8 -vga std \
>> -append "printk.time=0 clocksource=MIPS console=tty0 console=ttyS0 panic=-1" \
>> --no-reboot
>>
>> 100, 0, PASS, 5.258126, 100, 100, -
>> Results summary:
>> 0: 100 times (100.00%), avg time 6.508 (55.53 varience/7.45 deviation)
>> Ran command 100 times, 100 passes
>> ```
>>
>> With linux-next:
>> ```
>> ~/tmp/retry/retry.py -n 100 -c -- ./qemu-system-mips64el \
>> -display none -vga none -serial mon:stdio \
>> -machine malta -kernel ~/linux-next/vmlinux \
>> -cpu I6400 -smp 8 -vga std \
>> -append "printk.time=0 console=tty0 console=ttyS0 panic=-1" \
>> --no-reboot
>>
>> 100, 0, PASS, 4.507921, 100, 100, -
>> Results summary:
>> 0: 100 times (100.00%), avg time 4.233 (0.04 varience/0.21 deviation)
>> Ran command 100 times, 100 passes
>> ```
>>
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>> I'll leave the test case alone as it's already marked as
>> QEMU_TEST_FLAKY_TESTS
>
> We should ensure we have some testing enabled if we switch this on. Was
> the FLAKY test marked for MTTCG issues or something else?
Tracking history, I think it was because this issue is still popping up after
disabling MTTCG.
I'll try to upgrade kernel used in this test.
Thanks
- Jiaxun
>
>> ---
>> configs/targets/mips64el-softmmu.mak | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/configs/targets/mips64el-softmmu.mak b/configs/targets/mips64el-softmmu.mak
>> index 8d9ab3ddc4b1..199b1d909a7d 100644
>> --- a/configs/targets/mips64el-softmmu.mak
>> +++ b/configs/targets/mips64el-softmmu.mak
>> @@ -1,3 +1,4 @@
>> TARGET_ARCH=mips64
>> TARGET_BASE_ARCH=mips
>> +TARGET_SUPPORTS_MTTCG=y
>> TARGET_NEED_FDT=y
>>
>> ---
>> base-commit: 248f6f62df073a3b4158fd0093863ab885feabb5
>> change-id: 20240511-mips_mttcg-47a6b19074b3
>>
>> Best regards,
>
> --
> Alex Bennée
> Virtualisation Tech Lead @ Linaro
--
- Jiaxun
next prev parent reply other threads:[~2024-06-05 12:48 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-11 20:26 [PATCH] mips64el-softmmu: Enable MTTCG Jiaxun Yang
2024-06-03 15:26 ` Philippe Mathieu-Daudé
2024-06-03 18:15 ` Pierrick Bouvier
2024-06-04 10:18 ` Jiaxun Yang
2024-06-04 12:43 ` Alex Bennée
2024-06-05 12:47 ` Jiaxun Yang [this message]
2024-06-07 10:49 ` Jiaxun Yang
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