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Wed, 5 Jun 2024 08:47:30 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.11.0-alpha0-497-g97f96844c-fm-20240526.001-g97f96844 MIME-Version: 1.0 Message-Id: In-Reply-To: <87h6e8g9p3.fsf@draig.linaro.org> References: <20240511-mips_mttcg-v1-1-1b71d9b85234@flygoat.com> <87h6e8g9p3.fsf@draig.linaro.org> Date: Wed, 05 Jun 2024 13:47:10 +0100 From: "Jiaxun Yang" To: =?UTF-8?Q?Alex_Benn=C3=A9e?= Cc: "QEMU devel" , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= Subject: Re: [PATCH] mips64el-softmmu: Enable MTTCG Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=103.168.172.157; envelope-from=jiaxun.yang@flygoat.com; helo=fhigh6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org =E5=9C=A82024=E5=B9=B46=E6=9C=884=E6=97=A5=E5=85=AD=E6=9C=88 =E4=B8=8B=E5= =8D=881:43=EF=BC=8CAlex Benn=C3=A9e=E5=86=99=E9=81=93=EF=BC=9A [...] > > I'm a little uncomfortable about making the success of MTTCG depend on > the user options passed to the kernel. Yes, I agree, it sounds awkward. > > How come a non-icount run depends on how many instructions are being r= un > on each core? Why is time not based on the wallclock time and by > definition synced between all cores? That's the problem of Guest Kernel, the synchronisation mechanism is poo= rly written that relies on instruction latency too much. I have patch pendin= g to improve it at guest side, but we can't fix it in existing binary. This clock, CP0_Counter, as per ISA spec, is independent between cores a= nd needs to be synchronized by software. We can emulate it as a monotonic c= lock source and Linux should be happy with it, but that is violating ISA spec. > >> In non-MTTCG build, the execution is slow enough so kernel won't >> observe back drifts. >> >> Test results: >> >> With clocksource=3DMIPS >> ``` >> ~/tmp/retry/retry.py -n 100 -c -- ./qemu-system-mips64el \ >> -display none -vga none -serial mon:stdio \ >> -machine malta -kernel ./vmlinux-4.7.0-rc1.I6400 \ >> -cpu I6400 -smp 8 -vga std \ >> -append "printk.time=3D0 clocksource=3DMIPS console=3Dtty0 consol= e=3DttyS0 panic=3D-1" \ >> --no-reboot >> >> 100, 0, PASS, 5.258126, 100, 100, - >> Results summary: >> 0: 100 times (100.00%), avg time 6.508 (55.53 varience/7.45 deviation) >> Ran command 100 times, 100 passes >> ``` >> >> With linux-next: >> ``` >> ~/tmp/retry/retry.py -n 100 -c -- ./qemu-system-mips64el \ >> -display none -vga none -serial mon:stdio \ >> -machine malta -kernel ~/linux-next/vmlinux \ >> -cpu I6400 -smp 8 -vga std \ >> -append "printk.time=3D0 console=3Dtty0 console=3DttyS0 panic=3D-= 1" \ >> --no-reboot >> >> 100, 0, PASS, 4.507921, 100, 100, - >> Results summary: >> 0: 100 times (100.00%), avg time 4.233 (0.04 varience/0.21 deviation) >> Ran command 100 times, 100 passes >> ``` >> >> Signed-off-by: Jiaxun Yang >> --- >> I'll leave the test case alone as it's already marked as >> QEMU_TEST_FLAKY_TESTS > > We should ensure we have some testing enabled if we switch this on. Was > the FLAKY test marked for MTTCG issues or something else? Tracking history, I think it was because this issue is still popping up = after disabling MTTCG. I'll try to upgrade kernel used in this test. Thanks - Jiaxun > >> --- >> configs/targets/mips64el-softmmu.mak | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/configs/targets/mips64el-softmmu.mak b/configs/targets/m= ips64el-softmmu.mak >> index 8d9ab3ddc4b1..199b1d909a7d 100644 >> --- a/configs/targets/mips64el-softmmu.mak >> +++ b/configs/targets/mips64el-softmmu.mak >> @@ -1,3 +1,4 @@ >> TARGET_ARCH=3Dmips64 >> TARGET_BASE_ARCH=3Dmips >> +TARGET_SUPPORTS_MTTCG=3Dy >> TARGET_NEED_FDT=3Dy >> >> --- >> base-commit: 248f6f62df073a3b4158fd0093863ab885feabb5 >> change-id: 20240511-mips_mttcg-47a6b19074b3 >> >> Best regards, > > --=20 > Alex Benn=C3=A9e > Virtualisation Tech Lead @ Linaro --=20 - Jiaxun