From: Richard Henderson <richard.henderson@linaro.org>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com
Subject: Re: [PATCH 1/2] target/riscv/cpu: set cpu->cfg in register_cpu_props()
Date: Tue, 10 Jan 2023 21:39:16 -0800 [thread overview]
Message-ID: <cbc36e57-6a55-0c96-0170-ff4c0563d556@linaro.org> (raw)
In-Reply-To: <20230110201405.247785-2-dbarboza@ventanamicro.com>
On 1/10/23 12:14, Daniel Henrique Barboza wrote:
> +/*
> + * Register CPU props based on env.misa_ext. If a non-zero
> + * value was set, register only the required cpu->cfg.ext_*
> + * properties and leave. env.misa_ext = 0 means that we want
> + * all the default properties to be registered.
> + */
> static void register_cpu_props(DeviceState *dev)
Suggest invoking this as .instance_post_init hook on TYPE_RISCV_CPU.
Then you don't need to manually call it on every cpu class.
r~
next prev parent reply other threads:[~2023-01-11 5:40 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-10 20:14 [PATCH 0/2] target/riscv/cpu: fix sifive_u 32/64bits boot in riscv-to-apply.next Daniel Henrique Barboza
2023-01-10 20:14 ` [PATCH 1/2] target/riscv/cpu: set cpu->cfg in register_cpu_props() Daniel Henrique Barboza
2023-01-10 22:52 ` Alistair Francis
2023-01-11 5:39 ` Richard Henderson [this message]
2023-01-11 15:51 ` Daniel Henrique Barboza
2023-01-11 5:55 ` Bin Meng
2023-01-10 20:14 ` [PATCH 2/2] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() Daniel Henrique Barboza
2023-01-10 22:53 ` Alistair Francis
2023-01-11 5:56 ` Bin Meng
2023-01-10 22:27 ` [PATCH 0/2] target/riscv/cpu: fix sifive_u 32/64bits boot in riscv-to-apply.next Daniel Henrique Barboza
2023-01-11 5:01 ` Alistair Francis
2023-01-13 1:28 ` Bin Meng
2023-01-13 10:20 ` Daniel Henrique Barboza
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