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References: <20171013162438.32458-1-alex.bennee@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <cbd163be-fd12-9b58-c8cc-34f94c742e25@linaro.org>
Date: Mon, 16 Oct 2017 15:08:34 -0700
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Subject: Re: [Qemu-devel] [RFC PATCH 16/30] target/arm/translate-a64.c: add
 FP16 FADD/FMUL/FDIV to AdvSIMD 3 Same (!sub)
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To: =?UTF-8?Q?Alex_Benn=c3=a9e?= <alex.bennee@linaro.org>
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org

On 10/13/2017 09:24 AM, Alex Bennée wrote:
> +DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
> +DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
> +DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
> +DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
...
>          switch (fpopcode) {
> +        case 0x2: /* FADD */
> +            gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
> +            break;

Forgot FSUB with case 0x12?


r~