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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436611ea387sm460632015e9.6.2025.01.02.07.45.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Jan 2025 07:45:41 -0800 (PST) Message-ID: Date: Thu, 2 Jan 2025 16:45:40 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 10/16] hw/char/pl011: Check if receiver is enabled To: Peter Maydell Cc: qemu-devel@nongnu.org, =?UTF-8?Q?Marc-Andr=C3=A9_Lureau?= , =?UTF-8?Q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, Mark Cave-Ayland , Tong Ho , Manos Pitsidianakis , Richard Henderson References: <20240719181041.49545-1-philmd@linaro.org> <20240719181041.49545-11-philmd@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Peter, On 29/7/24 17:51, Peter Maydell wrote: > On Fri, 19 Jul 2024 at 19:11, Philippe Mathieu-Daudé wrote: >> >> Do not receive characters when UART or receiver are disabled. >> >> Signed-off-by: Philippe Mathieu-Daudé >> Reviewed-by: Richard Henderson >> --- >> hw/char/pl011.c | 7 +++++-- >> 1 file changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/hw/char/pl011.c b/hw/char/pl011.c >> index c76283dccf..0ce91c13d3 100644 >> --- a/hw/char/pl011.c >> +++ b/hw/char/pl011.c >> @@ -85,6 +85,7 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) >> #define CR_OUT1 (1 << 12) >> #define CR_RTS (1 << 11) >> #define CR_DTR (1 << 10) >> +#define CR_RXE (1 << 9) >> #define CR_TXE (1 << 8) >> #define CR_LBE (1 << 7) >> #define CR_UARTEN (1 << 0) >> @@ -481,9 +482,11 @@ static void pl011_write(void *opaque, hwaddr offset, >> static int pl011_can_receive(void *opaque) >> { >> PL011State *s = (PL011State *)opaque; >> - int r; >> + int r = 0; >> >> - r = s->read_count < pl011_get_fifo_depth(s); >> + if ((s->cr & CR_UARTEN) && (s->cr & CR_RXE)) { >> + r = s->read_count < pl011_get_fifo_depth(s); >> + } >> trace_pl011_can_receive(s->lcr, s->read_count, r); >> return r; > > I have a vague recollection of a previous conversation > where we discussed whether tightening up the UART-enable > checks would break existing only-tested-on-QEMU baremetal > simple example code. But I can't find it in my email > archive -- do you remember a discussion about this or > am I misremembering? The previous conversation is: https://lore.kernel.org/qemu-devel/CAFEAcA_7dkWB9qPkzYmW6_F1eaAet0PPk0PHywGS2EpAkFAsUQ@mail.gmail.com/ I understood 'my first assembly "Hello, World" program' has to keep working, which only uses the TX channel; and the boot-serial-qtest is fixed in a previous patch. Now I get you were thinking of a wider baremetal example code. I'll convert to GUEST_ERROR log level, similar to the TX path, since it is still relevant for developers who plan to run their guest code on real hardware. Regards, Phil.