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Fri, 29 Nov 2024 09:05:23 -0800 (PST) Received: from [192.168.68.110] ([187.101.65.72]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-725417fb9adsm3827007b3a.127.2024.11.29.09.05.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 Nov 2024 09:05:22 -0800 (PST) Message-ID: Date: Fri, 29 Nov 2024 14:05:18 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH-for-10.0 2/3] hw/char/riscv_htif: Explicit little-endian implementation To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Cc: Weiwei Li , Alistair Francis , =?UTF-8?Q?Marc-Andr=C3=A9_Lureau?= , Bin Meng , qemu-riscv@nongnu.org, Palmer Dabbelt , Paolo Bonzini , Liu Zhiwei References: <20241129154304.34946-1-philmd@linaro.org> <20241129154304.34946-3-philmd@linaro.org> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20241129154304.34946-3-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/29/24 12:43 PM, Philippe Mathieu-Daudé wrote: > Since our RISC-V system emulation is only built for little > endian, the HTIF device aims to interface with little endian > memory accesses, thus we can explicit htif_mm_ops:endianness > being DEVICE_LITTLE_ENDIAN. > > In that case tswap64() is equivalent to le64_to_cpu(), as in > "convert this 64-bit little-endian value into host cpu order". > Replace to simplify. > > Signed-off-by: Philippe Mathieu-Daudé > --- Reviewed-by: Daniel Henrique Barboza > hw/char/riscv_htif.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) > > diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c > index 0345088e8b3..3f84d8d6738 100644 > --- a/hw/char/riscv_htif.c > +++ b/hw/char/riscv_htif.c > @@ -29,7 +29,7 @@ > #include "qemu/timer.h" > #include "qemu/error-report.h" > #include "exec/address-spaces.h" > -#include "exec/tswap.h" > +#include "qemu/bswap.h" > #include "sysemu/dma.h" > #include "sysemu/runstate.h" > > @@ -212,11 +212,11 @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written) > } else { > uint64_t syscall[8]; > cpu_physical_memory_read(payload, syscall, sizeof(syscall)); > - if (tswap64(syscall[0]) == PK_SYS_WRITE && > - tswap64(syscall[1]) == HTIF_DEV_CONSOLE && > - tswap64(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) { > + if (le64_to_cpu(syscall[0]) == PK_SYS_WRITE && > + le64_to_cpu(syscall[1]) == HTIF_DEV_CONSOLE && > + le64_to_cpu(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) { > uint8_t ch; > - cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1); > + cpu_physical_memory_read(le64_to_cpu(syscall[2]), &ch, 1); > /* > * XXX this blocks entire thread. Rewrite to use > * qemu_chr_fe_write and background I/O callbacks > @@ -324,6 +324,7 @@ static void htif_mm_write(void *opaque, hwaddr addr, > static const MemoryRegionOps htif_mm_ops = { > .read = htif_mm_read, > .write = htif_mm_write, > + .endianness = DEVICE_LITTLE_ENDIAN, > }; > > HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,