From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
alistair23@gmail.com, chihmin.chao@sifive.com,
palmer@dabbelt.com
Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org, wxy194768@alibaba-inc.com
Subject: Re: [PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVState
Date: Tue, 11 Feb 2020 07:53:27 -0800 [thread overview]
Message-ID: <cc4d0b93-013f-5cf5-4ff4-248ab99eec70@linaro.org> (raw)
In-Reply-To: <20200210081240.11481-2-zhiwei_liu@c-sky.com>
On 2/10/20 8:12 AM, LIU Zhiwei wrote:
> The 32 vector registers will be viewed as a continuous memory block.
> It avoids the convension between element index and (regno,offset).
> Thus elements can be directly accessed by offset from the first vector
> base address.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu.h | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
I still don't think you need to put stuff into a sub-structure. These register
names are unique in the manual, and not subdivided there.
r~
next prev parent reply other threads:[~2020-02-11 15:54 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-10 8:12 [PATCH v4 0/4]target-riscv: support vector extension part 1 LIU Zhiwei
2020-02-10 8:12 ` [PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-02-11 15:53 ` Richard Henderson [this message]
2020-02-12 7:17 ` LIU Zhiwei
2020-02-10 8:12 ` [PATCH v4 2/4] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
2020-02-11 15:56 ` Richard Henderson
2020-02-12 7:19 ` LIU Zhiwei
2020-02-18 22:34 ` Alistair Francis
2020-02-19 0:46 ` LIU Zhiwei
2020-02-19 1:05 ` Alistair Francis
2020-02-10 8:12 ` [PATCH v4 3/4] target/riscv: support vector extension csr LIU Zhiwei
2020-02-11 16:11 ` Richard Henderson
2020-02-12 7:23 ` LIU Zhiwei
2020-02-10 8:12 ` [PATCH v4 4/4] target/riscv: add vector configure instruction LIU Zhiwei
2020-02-11 16:56 ` Richard Henderson
2020-02-12 8:09 ` LIU Zhiwei
2020-02-12 19:28 ` Richard Henderson
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