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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e2ab48c28sm227425395e9.18.2025.09.29.07.37.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Sep 2025 07:37:29 -0700 (PDT) Message-ID: Date: Mon, 29 Sep 2025 16:37:28 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/riscv: Fix endianness swap on compressed instructions Content-Language: en-US To: Valentin Haudiquet , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-trivial@nongnu.org, zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, alistair.francis@wdc.com, palmer@dabbelt.com, vhaudiquet , anjo@rev.ng References: <20250929115543.1648157-1-valentin.haudiquet@canonical.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250929115543.1648157-1-valentin.haudiquet@canonical.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=philmd@linaro.org; helo=mail-wm1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, On 29/9/25 13:55, Valentin Haudiquet wrote: > From: vhaudiquet > > Three instructions were not using the endianness swap flag, which resulted in a bug on big-endian architectures. I suppose you mean "big-endian host architectures". If so, please clarify. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3131 > Buglink: https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/2123828 > > Signed-off-by: Valentin Haudiquet > --- > target/riscv/insn_trans/trans_rvzce.c.inc | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc > index c77c2b927b..dd15af0f54 100644 > --- a/target/riscv/insn_trans/trans_rvzce.c.inc > +++ b/target/riscv/insn_trans/trans_rvzce.c.inc > @@ -88,13 +88,13 @@ static bool trans_c_lbu(DisasContext *ctx, arg_c_lbu *a) > static bool trans_c_lhu(DisasContext *ctx, arg_c_lhu *a) > { > REQUIRE_ZCB(ctx); > - return gen_load(ctx, a, MO_UW); > + return gen_load(ctx, a, MO_TEUW); NAck. Please do not use MO_TE* anymore. Use explicit endianness. So far all our RISC-V targets are little-endian: $ git grep TARGET_BIG_ENDIAN configs/targets/riscv* $ If you are not worried about RISCV core running in BE mode (as we currently don't check MSTATUS_[USM]BE bits), your change should be: - return gen_load(ctx, a, MO_UW); + return gen_load(ctx, a, MO_UW | MO_LE); > } Regards, Phil.