Re: [Qemu-devel] [PATCH] target/i386: Introduce Denverton CPU model

[Tao Xu <tao3.xu@intel.com>]

On 7/10/2019 12:20 AM, Xiaoyao Li wrote:
> On Tue, 2019-07-09 at 22:27 +0800, Tao Xu wrote:
>> On 7/9/2019 4:39 PM, Xiaoyao Li wrote:
>>> On 7/9/2019 12:44 PM, Tao Xu wrote:
>>>> Denverton-Server is the Atom Processor of Intel Harrisonville platform.
>>>>
>>>> For more information:
>>>> https://ark.intel.com/content/www/us/en/ark/products/\
>>>> codename/63508/denverton.html
>>>>
>>>> Signed-off-by: Tao Xu <tao3.xu@intel.com>
>>>> ---
>>>>    target/i386/cpu.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
>>>>    1 file changed, 45 insertions(+)
>>>>
>>>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>>>> index 805ce95247..4efaff9918 100644
>>>> --- a/target/i386/cpu.c
>>>> +++ b/target/i386/cpu.c
>>>> @@ -2471,6 +2471,51 @@ static X86CPUDefinition builtin_x86_defs[] = {
>>>>            .xlevel = 0x80000008,
>>>>            .model_id = "Intel Xeon Processor (Icelake)",
>>>>        },
>>>> +    {
>>>> +        .name = "Denverton-Server",
>>>> +        .level = 21,
>>>> +        .vendor = CPUID_VENDOR_INTEL,
>>>> +        .family = 6,
>>>> +        .model = 95,
>>>> +        .stepping = 1,
>>>> +        .features[FEAT_1_EDX] =
>>>> +            CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
>>>> +            CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
>>>> +            CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA |
>>>> CPUID_CMOV |
>>>> +            CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX |
>>>> CPUID_FXSR |
>>>> +            CPUID_SSE | CPUID_SSE2,
>>>> +        .features[FEAT_1_ECX] =
>>>> +            CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
>>>> +            CPUID_EXT_VMX | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 |
>>>> +            CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_X2APIC |
>>>> +            CPUID_EXT_MOVBE | CPUID_EXT_POPCNT |
>>>> CPUID_EXT_TSC_DEADLINE_TIMER |
>>>> +            CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
>>>> +        .features[FEAT_8000_0001_EDX] =
>>>> +            CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
>>>> +            CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
>>>> +        .features[FEAT_8000_0001_ECX] =
>>>> +            CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
>>>> +        .features[FEAT_7_0_EBX] =
>>>> +            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
>>>> CPUID_7_0_EBX_ERMS |
>>>> +            CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED |
>>>> CPUID_7_0_EBX_SMAP |
>>>> +            CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
>>>> +        .features[FEAT_7_0_EDX] =
>>>> +            CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
>>>> +            CPUID_7_0_EDX_SPEC_CTRL_SSBD,
>>>
>>> The output of CPUID_7_0:EDX is 0 in my Denverton machine, of which the
>>> stepping is 0 and microcode is 0xe.
>>>
>>> Maybe we need to remove these 3 flag in the initial Denverton cpu model
>>> and add these features as 2nd version alias as Denverton-Server-IBRS? (I
>>> don't if SPEC_CTRL_SSBD and ARCH_CAPABILITIES belong to IBRS, may be we
>>> need 3rd version for these?)
>>>
>>
>> I am wondering if we cover all the stepping of CPU, all existing CPU
>> model should be add initial stepping cpu model. The same circumstance
>> occurred before because Cascadelake CPU stepping 5 haven't AVX512_VNNI,
>> then updated to stepping 6. Denverton has been released in Q3'2017, the
>> customer may not use the early stepping machine.
>>
> Focusing on spec_ctrl, my question is: Does Denverton with stepping 1 have this
> feature regardless of microcode.
> 

OK I will check Denverton is affected and if it is the microcode to fix 
or hardware.