* [PULL 01/22] hw/ppc/ppc4xx_devs: Make code style fixes to UIC code
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
@ 2021-01-06 3:37 ` David Gibson
2021-01-06 3:37 ` [PULL 02/22] ppc: Convert PPC UIC to a QOM device David Gibson
` (22 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:37 UTC (permalink / raw)
To: peter.maydell, groug
Cc: Edgar E . Iglesias, Thomas Huth, Philippe Mathieu-Daudé,
qemu-devel, qemu-ppc, David Gibson
From: Peter Maydell <peter.maydell@linaro.org>
In a following commit we will move the PPC UIC implementation to
its own file in hw/intc. To prevent checkpatch complaining about that
code-motion, fix up the minor style issues first.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20201212001537.24520-2-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc4xx_devs.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index f1651e04d9..f2f9ca4ffe 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -105,7 +105,7 @@ struct ppcuic_t {
qemu_irq *irqs;
};
-static void ppcuic_trigger_irq (ppcuic_t *uic)
+static void ppcuic_trigger_irq(ppcuic_t *uic)
{
uint32_t ir, cr;
int start, end, inc, i;
@@ -156,26 +156,28 @@ static void ppcuic_trigger_irq (ppcuic_t *uic)
}
}
-static void ppcuic_set_irq (void *opaque, int irq_num, int level)
+static void ppcuic_set_irq(void *opaque, int irq_num, int level)
{
ppcuic_t *uic;
uint32_t mask, sr;
uic = opaque;
- mask = 1U << (31-irq_num);
+ mask = 1U << (31 - irq_num);
LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
" mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
__func__, irq_num, level,
uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
- if (irq_num < 0 || irq_num > 31)
+ if (irq_num < 0 || irq_num > 31) {
return;
+ }
sr = uic->uicsr;
/* Update status register */
if (uic->uictr & mask) {
/* Edge sensitive interrupt */
- if (level == 1)
+ if (level == 1) {
uic->uicsr |= mask;
+ }
} else {
/* Level sensitive interrupt */
if (level == 1) {
@@ -188,11 +190,12 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
}
LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
"%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
- if (sr != uic->uicsr)
+ if (sr != uic->uicsr) {
ppcuic_trigger_irq(uic);
+ }
}
-static uint32_t dcr_read_uic (void *opaque, int dcrn)
+static uint32_t dcr_read_uic(void *opaque, int dcrn)
{
ppcuic_t *uic;
uint32_t ret;
@@ -220,13 +223,15 @@ static uint32_t dcr_read_uic (void *opaque, int dcrn)
ret = uic->uicsr & uic->uicer;
break;
case DCR_UICVR:
- if (!uic->use_vectors)
+ if (!uic->use_vectors) {
goto no_read;
+ }
ret = uic->uicvr;
break;
case DCR_UICVCR:
- if (!uic->use_vectors)
+ if (!uic->use_vectors) {
goto no_read;
+ }
ret = uic->uicvcr;
break;
default:
@@ -238,7 +243,7 @@ static uint32_t dcr_read_uic (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_uic (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_uic(void *opaque, int dcrn, uint32_t val)
{
ppcuic_t *uic;
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 02/22] ppc: Convert PPC UIC to a QOM device
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
2021-01-06 3:37 ` [PULL 01/22] hw/ppc/ppc4xx_devs: Make code style fixes to UIC code David Gibson
@ 2021-01-06 3:37 ` David Gibson
2021-01-06 3:37 ` [PULL 03/22] hw/ppc/virtex_ml507: Drop use of ppcuic_init() David Gibson
` (21 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:37 UTC (permalink / raw)
To: peter.maydell, groug
Cc: Edgar E . Iglesias, David Gibson, qemu-ppc, qemu-devel
From: Peter Maydell <peter.maydell@linaro.org>
Currently the PPC UIC ("Universal Interrupt Controller") is implemented
as a non-QOM device in ppc4xx_devs.c. Convert it to a proper QOM device
in hw/intc.
The ppcuic_init() function is retained for the moment with its current
interface; in subsequent commits this will be tidied up to avoid the
allocation of an irq array.
This conversion adds VMState support.
It leaves the LOG_UIC() macro as-is to maximise the extent to which
this is simply code-movement rather than a rewrite (in new code it
would be better to use tracepoints).
The default property values for dcr-base and use-vectors are set to
match those use by most of our boards with a UIC.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20201212001537.24520-3-peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
MAINTAINERS | 2 +
hw/intc/Kconfig | 3 +
hw/intc/meson.build | 1 +
hw/intc/ppc-uic.c | 321 ++++++++++++++++++++++++++++++++++++++
hw/ppc/Kconfig | 1 +
hw/ppc/ppc4xx_devs.c | 267 ++++---------------------------
include/hw/intc/ppc-uic.h | 73 +++++++++
7 files changed, 431 insertions(+), 237 deletions(-)
create mode 100644 hw/intc/ppc-uic.c
create mode 100644 include/hw/intc/ppc-uic.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 42fedf91e7..edd11ab9c4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1680,6 +1680,8 @@ F: hw/ppc/ppc4*.c
F: hw/i2c/ppc4xx_i2c.c
F: include/hw/ppc/ppc4xx.h
F: include/hw/i2c/ppc4xx_i2c.h
+F: hw/intc/ppc-uic.c
+F: include/hw/intc/ppc-uic.h
Character devices
M: Marc-André Lureau <marcandre.lureau@redhat.com>
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index d07954086a..468d548ca7 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -62,6 +62,9 @@ config S390_FLIC_KVM
config OMPIC
bool
+config PPC_UIC
+ bool
+
config RX_ICU
bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 7c3e9daf58..68da782ad2 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -41,6 +41,7 @@ specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_intc.c'))
specific_ss.add(when: 'CONFIG_OMPIC', if_true: files('ompic.c'))
specific_ss.add(when: 'CONFIG_OPENPIC_KVM', if_true: files('openpic_kvm.c'))
specific_ss.add(when: 'CONFIG_POWERNV', if_true: files('xics_pnv.c', 'pnv_xive.c'))
+specific_ss.add(when: 'CONFIG_PPC_UIC', if_true: files('ppc-uic.c'))
specific_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_ic.c', 'bcm2836_control.c'))
specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
diff --git a/hw/intc/ppc-uic.c b/hw/intc/ppc-uic.c
new file mode 100644
index 0000000000..b21951eea8
--- /dev/null
+++ b/hw/intc/ppc-uic.c
@@ -0,0 +1,321 @@
+/*
+ * "Universal" Interrupt Controller for PowerPPC 4xx embedded processors
+ *
+ * Copyright (c) 2007 Jocelyn Mayer
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "include/hw/intc/ppc-uic.h"
+#include "hw/irq.h"
+#include "cpu.h"
+#include "hw/ppc/ppc.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
+
+enum {
+ DCR_UICSR = 0x000,
+ DCR_UICSRS = 0x001,
+ DCR_UICER = 0x002,
+ DCR_UICCR = 0x003,
+ DCR_UICPR = 0x004,
+ DCR_UICTR = 0x005,
+ DCR_UICMSR = 0x006,
+ DCR_UICVR = 0x007,
+ DCR_UICVCR = 0x008,
+ DCR_UICMAX = 0x009,
+};
+
+/*#define DEBUG_UIC*/
+
+#ifdef DEBUG_UIC
+# define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
+#else
+# define LOG_UIC(...) do { } while (0)
+#endif
+
+static void ppcuic_trigger_irq(PPCUIC *uic)
+{
+ uint32_t ir, cr;
+ int start, end, inc, i;
+
+ /* Trigger interrupt if any is pending */
+ ir = uic->uicsr & uic->uicer & (~uic->uiccr);
+ cr = uic->uicsr & uic->uicer & uic->uiccr;
+ LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
+ " uiccr %08" PRIx32 "\n"
+ " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
+ __func__, uic->uicsr, uic->uicer, uic->uiccr,
+ uic->uicsr & uic->uicer, ir, cr);
+ if (ir != 0x0000000) {
+ LOG_UIC("Raise UIC interrupt\n");
+ qemu_irq_raise(uic->output_int);
+ } else {
+ LOG_UIC("Lower UIC interrupt\n");
+ qemu_irq_lower(uic->output_int);
+ }
+ /* Trigger critical interrupt if any is pending and update vector */
+ if (cr != 0x0000000) {
+ qemu_irq_raise(uic->output_cint);
+ if (uic->use_vectors) {
+ /* Compute critical IRQ vector */
+ if (uic->uicvcr & 1) {
+ start = 31;
+ end = 0;
+ inc = -1;
+ } else {
+ start = 0;
+ end = 31;
+ inc = 1;
+ }
+ uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
+ for (i = start; i <= end; i += inc) {
+ if (cr & (1 << i)) {
+ uic->uicvr += (i - start) * 512 * inc;
+ break;
+ }
+ }
+ }
+ LOG_UIC("Raise UIC critical interrupt - "
+ "vector %08" PRIx32 "\n", uic->uicvr);
+ } else {
+ LOG_UIC("Lower UIC critical interrupt\n");
+ qemu_irq_lower(uic->output_cint);
+ uic->uicvr = 0x00000000;
+ }
+}
+
+static void ppcuic_set_irq(void *opaque, int irq_num, int level)
+{
+ PPCUIC *uic;
+ uint32_t mask, sr;
+
+ uic = opaque;
+ mask = 1U << (31 - irq_num);
+ LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
+ " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
+ __func__, irq_num, level,
+ uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
+ if (irq_num < 0 || irq_num > 31) {
+ return;
+ }
+ sr = uic->uicsr;
+
+ /* Update status register */
+ if (uic->uictr & mask) {
+ /* Edge sensitive interrupt */
+ if (level == 1) {
+ uic->uicsr |= mask;
+ }
+ } else {
+ /* Level sensitive interrupt */
+ if (level == 1) {
+ uic->uicsr |= mask;
+ uic->level |= mask;
+ } else {
+ uic->uicsr &= ~mask;
+ uic->level &= ~mask;
+ }
+ }
+ LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
+ "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
+ if (sr != uic->uicsr) {
+ ppcuic_trigger_irq(uic);
+ }
+}
+
+static uint32_t dcr_read_uic(void *opaque, int dcrn)
+{
+ PPCUIC *uic;
+ uint32_t ret;
+
+ uic = opaque;
+ dcrn -= uic->dcr_base;
+ switch (dcrn) {
+ case DCR_UICSR:
+ case DCR_UICSRS:
+ ret = uic->uicsr;
+ break;
+ case DCR_UICER:
+ ret = uic->uicer;
+ break;
+ case DCR_UICCR:
+ ret = uic->uiccr;
+ break;
+ case DCR_UICPR:
+ ret = uic->uicpr;
+ break;
+ case DCR_UICTR:
+ ret = uic->uictr;
+ break;
+ case DCR_UICMSR:
+ ret = uic->uicsr & uic->uicer;
+ break;
+ case DCR_UICVR:
+ if (!uic->use_vectors) {
+ goto no_read;
+ }
+ ret = uic->uicvr;
+ break;
+ case DCR_UICVCR:
+ if (!uic->use_vectors) {
+ goto no_read;
+ }
+ ret = uic->uicvcr;
+ break;
+ default:
+ no_read:
+ ret = 0x00000000;
+ break;
+ }
+
+ return ret;
+}
+
+static void dcr_write_uic(void *opaque, int dcrn, uint32_t val)
+{
+ PPCUIC *uic;
+
+ uic = opaque;
+ dcrn -= uic->dcr_base;
+ LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
+ switch (dcrn) {
+ case DCR_UICSR:
+ uic->uicsr &= ~val;
+ uic->uicsr |= uic->level;
+ ppcuic_trigger_irq(uic);
+ break;
+ case DCR_UICSRS:
+ uic->uicsr |= val;
+ ppcuic_trigger_irq(uic);
+ break;
+ case DCR_UICER:
+ uic->uicer = val;
+ ppcuic_trigger_irq(uic);
+ break;
+ case DCR_UICCR:
+ uic->uiccr = val;
+ ppcuic_trigger_irq(uic);
+ break;
+ case DCR_UICPR:
+ uic->uicpr = val;
+ break;
+ case DCR_UICTR:
+ uic->uictr = val;
+ ppcuic_trigger_irq(uic);
+ break;
+ case DCR_UICMSR:
+ break;
+ case DCR_UICVR:
+ break;
+ case DCR_UICVCR:
+ uic->uicvcr = val & 0xFFFFFFFD;
+ ppcuic_trigger_irq(uic);
+ break;
+ }
+}
+
+static void ppc_uic_reset(DeviceState *dev)
+{
+ PPCUIC *uic = PPC_UIC(dev);
+
+ uic->uiccr = 0x00000000;
+ uic->uicer = 0x00000000;
+ uic->uicpr = 0x00000000;
+ uic->uicsr = 0x00000000;
+ uic->uictr = 0x00000000;
+ if (uic->use_vectors) {
+ uic->uicvcr = 0x00000000;
+ uic->uicvr = 0x0000000;
+ }
+}
+
+static void ppc_uic_realize(DeviceState *dev, Error **errp)
+{
+ PPCUIC *uic = PPC_UIC(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ PowerPCCPU *cpu;
+ int i;
+
+ if (!uic->cpu) {
+ /* This is a programming error in the code using this device */
+ error_setg(errp, "ppc-uic 'cpu' link property was not set");
+ return;
+ }
+
+ cpu = POWERPC_CPU(uic->cpu);
+ for (i = 0; i < DCR_UICMAX; i++) {
+ ppc_dcr_register(&cpu->env, uic->dcr_base + i, uic,
+ &dcr_read_uic, &dcr_write_uic);
+ }
+
+ sysbus_init_irq(sbd, &uic->output_int);
+ sysbus_init_irq(sbd, &uic->output_cint);
+ qdev_init_gpio_in(dev, ppcuic_set_irq, UIC_MAX_IRQ);
+}
+
+static Property ppc_uic_properties[] = {
+ DEFINE_PROP_LINK("cpu", PPCUIC, cpu, TYPE_CPU, CPUState *),
+ DEFINE_PROP_UINT32("dcr-base", PPCUIC, dcr_base, 0x30),
+ DEFINE_PROP_BOOL("use-vectors", PPCUIC, use_vectors, true),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static const VMStateDescription ppc_uic_vmstate = {
+ .name = "ppc-uic",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(level, PPCUIC),
+ VMSTATE_UINT32(uicsr, PPCUIC),
+ VMSTATE_UINT32(uicer, PPCUIC),
+ VMSTATE_UINT32(uiccr, PPCUIC),
+ VMSTATE_UINT32(uicpr, PPCUIC),
+ VMSTATE_UINT32(uictr, PPCUIC),
+ VMSTATE_UINT32(uicvcr, PPCUIC),
+ VMSTATE_UINT32(uicvr, PPCUIC),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static void ppc_uic_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = ppc_uic_reset;
+ dc->realize = ppc_uic_realize;
+ dc->vmsd = &ppc_uic_vmstate;
+ device_class_set_props(dc, ppc_uic_properties);
+}
+
+static const TypeInfo ppc_uic_info = {
+ .name = TYPE_PPC_UIC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PPCUIC),
+ .class_init = ppc_uic_class_init,
+};
+
+static void ppc_uic_register_types(void)
+{
+ type_register_static(&ppc_uic_info);
+}
+
+type_init(ppc_uic_register_types);
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index dd86e664d2..982d55f587 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -53,6 +53,7 @@ config PPC4XX
bool
select BITBANG_I2C
select PCI
+ select PPC_UIC
config SAM460EX
bool
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index f2f9ca4ffe..ffe4cf43e8 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -30,9 +30,12 @@
#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/boards.h"
+#include "hw/intc/ppc-uic.h"
+#include "hw/qdev-properties.h"
#include "qemu/log.h"
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
+#include "qapi/error.h"
/*#define DEBUG_UIC*/
@@ -76,250 +79,40 @@ PowerPCCPU *ppc4xx_init(const char *cpu_type,
/*****************************************************************************/
/* "Universal" Interrupt controller */
-enum {
- DCR_UICSR = 0x000,
- DCR_UICSRS = 0x001,
- DCR_UICER = 0x002,
- DCR_UICCR = 0x003,
- DCR_UICPR = 0x004,
- DCR_UICTR = 0x005,
- DCR_UICMSR = 0x006,
- DCR_UICVR = 0x007,
- DCR_UICVCR = 0x008,
- DCR_UICMAX = 0x009,
-};
-
-#define UIC_MAX_IRQ 32
-typedef struct ppcuic_t ppcuic_t;
-struct ppcuic_t {
- uint32_t dcr_base;
- int use_vectors;
- uint32_t level; /* Remembers the state of level-triggered interrupts. */
- uint32_t uicsr; /* Status register */
- uint32_t uicer; /* Enable register */
- uint32_t uiccr; /* Critical register */
- uint32_t uicpr; /* Polarity register */
- uint32_t uictr; /* Triggering register */
- uint32_t uicvcr; /* Vector configuration register */
- uint32_t uicvr;
- qemu_irq *irqs;
-};
-
-static void ppcuic_trigger_irq(ppcuic_t *uic)
-{
- uint32_t ir, cr;
- int start, end, inc, i;
-
- /* Trigger interrupt if any is pending */
- ir = uic->uicsr & uic->uicer & (~uic->uiccr);
- cr = uic->uicsr & uic->uicer & uic->uiccr;
- LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
- " uiccr %08" PRIx32 "\n"
- " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
- __func__, uic->uicsr, uic->uicer, uic->uiccr,
- uic->uicsr & uic->uicer, ir, cr);
- if (ir != 0x0000000) {
- LOG_UIC("Raise UIC interrupt\n");
- qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
- } else {
- LOG_UIC("Lower UIC interrupt\n");
- qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
- }
- /* Trigger critical interrupt if any is pending and update vector */
- if (cr != 0x0000000) {
- qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
- if (uic->use_vectors) {
- /* Compute critical IRQ vector */
- if (uic->uicvcr & 1) {
- start = 31;
- end = 0;
- inc = -1;
- } else {
- start = 0;
- end = 31;
- inc = 1;
- }
- uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
- for (i = start; i <= end; i += inc) {
- if (cr & (1 << i)) {
- uic->uicvr += (i - start) * 512 * inc;
- break;
- }
- }
- }
- LOG_UIC("Raise UIC critical interrupt - "
- "vector %08" PRIx32 "\n", uic->uicvr);
- } else {
- LOG_UIC("Lower UIC critical interrupt\n");
- qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
- uic->uicvr = 0x00000000;
- }
-}
-
-static void ppcuic_set_irq(void *opaque, int irq_num, int level)
-{
- ppcuic_t *uic;
- uint32_t mask, sr;
-
- uic = opaque;
- mask = 1U << (31 - irq_num);
- LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
- " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
- __func__, irq_num, level,
- uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
- if (irq_num < 0 || irq_num > 31) {
- return;
- }
- sr = uic->uicsr;
-
- /* Update status register */
- if (uic->uictr & mask) {
- /* Edge sensitive interrupt */
- if (level == 1) {
- uic->uicsr |= mask;
- }
- } else {
- /* Level sensitive interrupt */
- if (level == 1) {
- uic->uicsr |= mask;
- uic->level |= mask;
- } else {
- uic->uicsr &= ~mask;
- uic->level &= ~mask;
- }
- }
- LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
- "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
- if (sr != uic->uicsr) {
- ppcuic_trigger_irq(uic);
- }
-}
-
-static uint32_t dcr_read_uic(void *opaque, int dcrn)
-{
- ppcuic_t *uic;
- uint32_t ret;
-
- uic = opaque;
- dcrn -= uic->dcr_base;
- switch (dcrn) {
- case DCR_UICSR:
- case DCR_UICSRS:
- ret = uic->uicsr;
- break;
- case DCR_UICER:
- ret = uic->uicer;
- break;
- case DCR_UICCR:
- ret = uic->uiccr;
- break;
- case DCR_UICPR:
- ret = uic->uicpr;
- break;
- case DCR_UICTR:
- ret = uic->uictr;
- break;
- case DCR_UICMSR:
- ret = uic->uicsr & uic->uicer;
- break;
- case DCR_UICVR:
- if (!uic->use_vectors) {
- goto no_read;
- }
- ret = uic->uicvr;
- break;
- case DCR_UICVCR:
- if (!uic->use_vectors) {
- goto no_read;
- }
- ret = uic->uicvcr;
- break;
- default:
- no_read:
- ret = 0x00000000;
- break;
- }
-
- return ret;
-}
-
-static void dcr_write_uic(void *opaque, int dcrn, uint32_t val)
-{
- ppcuic_t *uic;
-
- uic = opaque;
- dcrn -= uic->dcr_base;
- LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
- switch (dcrn) {
- case DCR_UICSR:
- uic->uicsr &= ~val;
- uic->uicsr |= uic->level;
- ppcuic_trigger_irq(uic);
- break;
- case DCR_UICSRS:
- uic->uicsr |= val;
- ppcuic_trigger_irq(uic);
- break;
- case DCR_UICER:
- uic->uicer = val;
- ppcuic_trigger_irq(uic);
- break;
- case DCR_UICCR:
- uic->uiccr = val;
- ppcuic_trigger_irq(uic);
- break;
- case DCR_UICPR:
- uic->uicpr = val;
- break;
- case DCR_UICTR:
- uic->uictr = val;
- ppcuic_trigger_irq(uic);
- break;
- case DCR_UICMSR:
- break;
- case DCR_UICVR:
- break;
- case DCR_UICVCR:
- uic->uicvcr = val & 0xFFFFFFFD;
- ppcuic_trigger_irq(uic);
- break;
- }
-}
-
-static void ppcuic_reset (void *opaque)
-{
- ppcuic_t *uic;
-
- uic = opaque;
- uic->uiccr = 0x00000000;
- uic->uicer = 0x00000000;
- uic->uicpr = 0x00000000;
- uic->uicsr = 0x00000000;
- uic->uictr = 0x00000000;
- if (uic->use_vectors) {
- uic->uicvcr = 0x00000000;
- uic->uicvr = 0x0000000;
- }
-}
qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr)
{
- ppcuic_t *uic;
+ DeviceState *uicdev = qdev_new(TYPE_PPC_UIC);
+ SysBusDevice *uicsbd = SYS_BUS_DEVICE(uicdev);
+ qemu_irq *uic_irqs;
int i;
- uic = g_malloc0(sizeof(ppcuic_t));
- uic->dcr_base = dcr_base;
- uic->irqs = irqs;
- if (has_vr)
- uic->use_vectors = 1;
- for (i = 0; i < DCR_UICMAX; i++) {
- ppc_dcr_register(env, dcr_base + i, uic,
- &dcr_read_uic, &dcr_write_uic);
+ qdev_prop_set_uint32(uicdev, "dcr-base", dcr_base);
+ qdev_prop_set_bit(uicdev, "use-vectors", has_vr);
+ object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(env_cpu(env)),
+ &error_fatal);
+ sysbus_realize_and_unref(uicsbd, &error_fatal);
+
+ sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, irqs[PPCUIC_OUTPUT_INT]);
+ sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, irqs[PPCUIC_OUTPUT_CINT]);
+
+ /*
+ * Return an allocated array of the UIC's input IRQ lines.
+ * This is an ugly temporary API to retain compatibility with
+ * the ppcuic_init() interface from the pre-QOM-conversion UIC.
+ * None of the callers free this array, so it is leaked -- but
+ * so was the array allocated by qemu_allocate_irqs() in the
+ * old code.
+ *
+ * The callers should just instantiate the UIC and wire it up
+ * themselves rather than passing qemu_irq* in and out of this function.
+ */
+ uic_irqs = g_new0(qemu_irq, UIC_MAX_IRQ);
+ for (i = 0; i < UIC_MAX_IRQ; i++) {
+ uic_irqs[i] = qdev_get_gpio_in(uicdev, i);
}
- qemu_register_reset(ppcuic_reset, uic);
-
- return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
+ return uic_irqs;
}
/*****************************************************************************/
diff --git a/include/hw/intc/ppc-uic.h b/include/hw/intc/ppc-uic.h
new file mode 100644
index 0000000000..e614e2ffd8
--- /dev/null
+++ b/include/hw/intc/ppc-uic.h
@@ -0,0 +1,73 @@
+/*
+ * "Universal" Interrupt Controller for PowerPPC 4xx embedded processors
+ *
+ * Copyright (c) 2007 Jocelyn Mayer
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_INTC_PPC_UIC_H
+#define HW_INTC_PPC_UIC_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_PPC_UIC "ppc-uic"
+OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC)
+
+/*
+ * QEMU interface:
+ * QOM property "cpu": link to the PPC CPU
+ * (no default, must be set)
+ * QOM property "dcr-base": base of the bank of DCR registers for the UIC
+ * (default 0x30)
+ * QOM property "use-vectors": true if the UIC has vector registers
+ * (default true)
+ * unnamed GPIO inputs 0..UIC_MAX_IRQ: input IRQ lines
+ * sysbus IRQs:
+ * 0 (PPCUIC_OUTPUT_INT): output INT line to the CPU
+ * 1 (PPCUIC_OUTPUT_CINT): output CINT line to the CPU
+ */
+
+#define UIC_MAX_IRQ 32
+
+struct PPCUIC {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ qemu_irq output_int;
+ qemu_irq output_cint;
+
+ /* properties */
+ CPUState *cpu;
+ uint32_t dcr_base;
+ bool use_vectors;
+
+ uint32_t level; /* Remembers the state of level-triggered interrupts. */
+ uint32_t uicsr; /* Status register */
+ uint32_t uicer; /* Enable register */
+ uint32_t uiccr; /* Critical register */
+ uint32_t uicpr; /* Polarity register */
+ uint32_t uictr; /* Triggering register */
+ uint32_t uicvcr; /* Vector configuration register */
+ uint32_t uicvr;
+};
+
+#endif
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 03/22] hw/ppc/virtex_ml507: Drop use of ppcuic_init()
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
2021-01-06 3:37 ` [PULL 01/22] hw/ppc/ppc4xx_devs: Make code style fixes to UIC code David Gibson
2021-01-06 3:37 ` [PULL 02/22] ppc: Convert PPC UIC to a QOM device David Gibson
@ 2021-01-06 3:37 ` David Gibson
2021-01-06 3:37 ` [PULL 04/22] hw/ppc/ppc440_bamboo: " David Gibson
` (20 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:37 UTC (permalink / raw)
To: peter.maydell, groug
Cc: Edgar E . Iglesias, David Gibson, qemu-ppc, qemu-devel
From: Peter Maydell <peter.maydell@linaro.org>
Switch the virtex_ml507 board to directly creating and
configuring the UIC, rather than doing it via the old
ppcuic_init() helper function.
This fixes a trivial Coverity-detected memory leak where
we were leaking the array of IRQs returned by ppcuic_init().
Fixes: Coverity CID 1421992
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20201212001537.24520-4-peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/virtex_ml507.c | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
index 07fe49da0d..b26ff17767 100644
--- a/hw/ppc/virtex_ml507.c
+++ b/hw/ppc/virtex_ml507.c
@@ -43,6 +43,7 @@
#include "qemu/option.h"
#include "exec/address-spaces.h"
+#include "hw/intc/ppc-uic.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/qdev-properties.h"
@@ -95,7 +96,8 @@ static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk)
{
PowerPCCPU *cpu;
CPUPPCState *env;
- qemu_irq *irqs;
+ DeviceState *uicdev;
+ SysBusDevice *uicsbd;
cpu = POWERPC_CPU(cpu_create(cpu_type));
env = &cpu->env;
@@ -105,10 +107,19 @@ static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk)
ppc_dcr_init(env, NULL, NULL);
/* interrupt controller */
- irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB);
- irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
- irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
- ppcuic_init(env, irqs, 0x0C0, 0, 1);
+ uicdev = qdev_new(TYPE_PPC_UIC);
+ uicsbd = SYS_BUS_DEVICE(uicdev);
+
+ object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
+ &error_fatal);
+ sysbus_realize_and_unref(uicsbd, &error_fatal);
+
+ sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
+ ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
+ sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
+ ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
+
+ /* This board doesn't wire anything up to the inputs of the UIC. */
return cpu;
}
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 04/22] hw/ppc/ppc440_bamboo: Drop use of ppcuic_init()
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (2 preceding siblings ...)
2021-01-06 3:37 ` [PULL 03/22] hw/ppc/virtex_ml507: Drop use of ppcuic_init() David Gibson
@ 2021-01-06 3:37 ` David Gibson
2021-01-06 3:37 ` [PULL 05/22] spapr: DRC lookup cannot fail David Gibson
` (19 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:37 UTC (permalink / raw)
To: peter.maydell, groug; +Cc: David Gibson, qemu-ppc, qemu-devel
From: Peter Maydell <peter.maydell@linaro.org>
Switch the bamboo board to directly creating and configuring the UIC,
rather than doing it via the old ppcuic_init() helper function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20201212001537.24520-5-peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc440_bamboo.c | 38 +++++++++++++++++++++++++++-----------
1 file changed, 27 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 665bc1784e..b156bcb999 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -33,6 +33,9 @@
#include "sysemu/qtest.h"
#include "sysemu/reset.h"
#include "hw/sysbus.h"
+#include "hw/intc/ppc-uic.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
#define BINARY_DEVICE_TREE_FILE "bamboo.dtb"
@@ -168,13 +171,13 @@ static void bamboo_init(MachineState *machine)
MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS);
hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
- qemu_irq *pic;
- qemu_irq *irqs;
PCIBus *pcibus;
PowerPCCPU *cpu;
CPUPPCState *env;
target_long initrd_size = 0;
DeviceState *dev;
+ DeviceState *uicdev;
+ SysBusDevice *uicsbd;
int success;
int i;
@@ -192,10 +195,17 @@ static void bamboo_init(MachineState *machine)
ppc_dcr_init(env, NULL, NULL);
/* interrupt controller */
- irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB);
- irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
- irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
- pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
+ uicdev = qdev_new(TYPE_PPC_UIC);
+ uicsbd = SYS_BUS_DEVICE(uicdev);
+
+ object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
+ &error_fatal);
+ sysbus_realize_and_unref(uicsbd, &error_fatal);
+
+ sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
+ ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
+ sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
+ ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
/* SDRAM controller */
memset(ram_bases, 0, sizeof(ram_bases));
@@ -203,14 +213,18 @@ static void bamboo_init(MachineState *machine)
ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
- ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
+ ppc4xx_sdram_init(env,
+ qdev_get_gpio_in(uicdev, 14),
+ PPC440EP_SDRAM_NR_BANKS, ram_memories,
ram_bases, ram_sizes, 1);
/* PCI */
dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
PPC440EP_PCI_CONFIG,
- pic[pci_irq_nrs[0]], pic[pci_irq_nrs[1]],
- pic[pci_irq_nrs[2]], pic[pci_irq_nrs[3]],
+ qdev_get_gpio_in(uicdev, pci_irq_nrs[0]),
+ qdev_get_gpio_in(uicdev, pci_irq_nrs[1]),
+ qdev_get_gpio_in(uicdev, pci_irq_nrs[2]),
+ qdev_get_gpio_in(uicdev, pci_irq_nrs[3]),
NULL);
pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
if (!pcibus) {
@@ -223,12 +237,14 @@ static void bamboo_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa);
if (serial_hd(0) != NULL) {
- serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
+ serial_mm_init(address_space_mem, 0xef600300, 0,
+ qdev_get_gpio_in(uicdev, 0),
PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
DEVICE_BIG_ENDIAN);
}
if (serial_hd(1) != NULL) {
- serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
+ serial_mm_init(address_space_mem, 0xef600400, 0,
+ qdev_get_gpio_in(uicdev, 1),
PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
DEVICE_BIG_ENDIAN);
}
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 05/22] spapr: DRC lookup cannot fail
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (3 preceding siblings ...)
2021-01-06 3:37 ` [PULL 04/22] hw/ppc/ppc440_bamboo: " David Gibson
@ 2021-01-06 3:37 ` David Gibson
2021-01-06 3:38 ` [PULL 06/22] spapr/xive: Make spapr_xive_pic_print_info() static David Gibson
` (18 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:37 UTC (permalink / raw)
To: peter.maydell, groug; +Cc: David Gibson, qemu-ppc, qemu-devel
From: Greg Kurz <groug@kaod.org>
All memory DRC objects are created during machine init. It is thus safe
to assume spapr_drc_by_id() cannot return NULL when hot-plug/unplugging
memory.
Make this clear with an assertion, like the code already does a few lines
above when looping over memory DRCs. This fixes Coverity reports 1437757
and 1437758.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <160805381160.228955.5388294067094240175.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 489cefcb81..08f57f9164 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -3437,6 +3437,7 @@ static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
if (dedicated_hp_event_source) {
drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
addr_start / SPAPR_MEMORY_BLOCK_SIZE);
+ g_assert(drc);
spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
nr_lmbs,
spapr_drc_index(drc));
@@ -3677,6 +3678,7 @@ static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
addr_start / SPAPR_MEMORY_BLOCK_SIZE);
+ g_assert(drc);
spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
nr_lmbs, spapr_drc_index(drc));
}
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 06/22] spapr/xive: Make spapr_xive_pic_print_info() static
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (4 preceding siblings ...)
2021-01-06 3:37 ` [PULL 05/22] spapr: DRC lookup cannot fail David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 07/22] spapr: Fix DR properties of the root node David Gibson
` (17 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug
Cc: Cédric Le Goater, David Gibson, qemu-ppc, qemu-devel
From: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20201215174025.2636824-1-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/spapr_xive.c | 2 +-
include/hw/ppc/spapr_xive.h | 2 --
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index caedd312d7..801bc19341 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -156,7 +156,7 @@ static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end,
#define spapr_xive_in_kernel(xive) \
(kvm_irqchip_in_kernel() && (xive)->fd != -1)
-void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon)
+static void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon)
{
XiveSource *xsrc = &xive->source;
int i;
diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h
index 26c8d90d71..b282960ad9 100644
--- a/include/hw/ppc/spapr_xive.h
+++ b/include/hw/ppc/spapr_xive.h
@@ -66,8 +66,6 @@ typedef struct SpaprXiveClass {
*/
#define SPAPR_XIVE_BLOCK_ID 0x0
-void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon);
-
struct SpaprMachineState;
void spapr_xive_hcall_init(struct SpaprMachineState *spapr);
void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable);
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 07/22] spapr: Fix DR properties of the root node
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (5 preceding siblings ...)
2021-01-06 3:38 ` [PULL 06/22] spapr/xive: Make spapr_xive_pic_print_info() static David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 08/22] spapr: Allow memory unplug to always succeed David Gibson
` (16 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug; +Cc: David Gibson, qemu-ppc, qemu-devel
From: Greg Kurz <groug@kaod.org>
Section 13.5.2 of LoPAPR mandates various DR related indentifiers
for all hot-pluggable entities to be exposed in the "ibm,drc-indexes",
"ibm,drc-power-domains", "ibm,drc-names" and "ibm,drc-types" properties
of their parent node. These properties are created with spapr_dt_drc().
PHBs and LMBs are both children of the machine. Their DR identifiers
are thus supposed to be exposed in the afore mentioned properties of
the root node.
When PHB hot-plug support was added, an extra call to spapr_dt_drc()
was introduced: this overwrites the existing properties, previously
populated with the LMB identifiers, and they end up containing only
PHB identifiers. This went unseen so far because linux doesn't care,
but this is still not conformant with LoPAPR.
Fortunately spapr_dt_drc() is able to handle multiple DR entity types
at the same time. Use that to handle DR indentifiers for PHBs and LMBs
with a single call to spapr_dt_drc(). While here also account for PMEM
DR identifiers, which were forgotten when NVDIMM hot-plug support was
added. Also add an assert to prevent further misuse of spapr_dt_drc().
With -m 1G,maxmem=2G,slots=8 passed on the QEMU command line we get:
Without this patch:
/proc/device-tree/ibm,drc-indexes
0000001f 20000001 20000002 20000003
20000000 20000005 20000006 20000007
20000004 20000009 20000008 20000010
20000011 20000012 20000013 20000014
20000015 20000016 20000017 20000018
20000019 2000000a 2000000b 2000000c
2000000d 2000000e 2000000f 2000001a
2000001b 2000001c 2000001d 2000001e
These are the DRC indexes for the 31 possible PHBs.
With this patch:
/proc/device-tree/ibm,drc-indexes
0000002b 90000000 90000001 90000002
90000003 90000004 90000005 90000006
90000007 20000001 20000002 20000003
20000000 20000005 20000006 20000007
20000004 20000009 20000008 20000010
20000011 20000012 20000013 20000014
20000015 20000016 20000017 20000018
20000019 2000000a 2000000b 2000000c
2000000d 2000000e 2000000f 2000001a
2000001b 2000001c 2000001d 2000001e
80000004 80000005 80000006 80000007
And now we also have the 4 ((2G - 1G) / 256M) LMBs and the
8 (slots) PMEMs.
Fixes: 3998ccd09298 ("spapr: populate PHB DRC entries for root DT node")
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <160794479566.35245.17809158217760761558.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 21 ++++++++++++---------
hw/ppc/spapr_drc.c | 6 ++++++
2 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 08f57f9164..68a3ceb927 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1120,6 +1120,7 @@ void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space)
MachineState *machine = MACHINE(spapr);
MachineClass *mc = MACHINE_GET_CLASS(machine);
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
+ uint32_t root_drc_type_mask = 0;
int ret;
void *fdt;
SpaprPhbState *phb;
@@ -1194,8 +1195,18 @@ void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space)
spapr_dt_cpus(fdt, spapr);
+ /* ibm,drc-indexes and friends */
if (smc->dr_lmb_enabled) {
- _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
+ root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB;
+ }
+ if (smc->dr_phb_enabled) {
+ root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB;
+ }
+ if (mc->nvdimm_supported) {
+ root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM;
+ }
+ if (root_drc_type_mask) {
+ _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask));
}
if (mc->has_hotpluggable_cpus) {
@@ -1233,14 +1244,6 @@ void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space)
}
}
- if (smc->dr_phb_enabled) {
- ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB);
- if (ret < 0) {
- error_report("Couldn't set up PHB DR device tree properties");
- exit(1);
- }
- }
-
/* NVDIMM devices */
if (mc->nvdimm_supported) {
spapr_dt_persistent_memory(spapr, fdt);
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index f991cf89a0..fc7e321fcd 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -832,6 +832,12 @@ int spapr_dt_drc(void *fdt, int offset, Object *owner, uint32_t drc_type_mask)
GString *drc_names, *drc_types;
int ret;
+ /*
+ * This should really be only called once per node since it overwrites
+ * the OF properties if they already exist.
+ */
+ g_assert(!fdt_get_property(fdt, offset, "ibm,drc-indexes", NULL));
+
/* the first entry of each properties is a 32-bit integer encoding
* the number of elements in the array. we won't know this until
* we complete the iteration through all the matching DRCs, but
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 08/22] spapr: Allow memory unplug to always succeed
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (6 preceding siblings ...)
2021-01-06 3:38 ` [PULL 07/22] spapr: Fix DR properties of the root node David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 09/22] spapr: Fix buffer overflow in spapr_numa_associativity_init() David Gibson
` (15 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug; +Cc: David Gibson, qemu-ppc, qemu-devel
From: Greg Kurz <groug@kaod.org>
It is currently impossible to hot-unplug a memory device between
machine reset and CAS.
(qemu) device_del dimm1
Error: Memory hot unplug not supported for this guest
This limitation was introduced in order to provide an explicit
error path for older guests that didn't support hot-plug event
sources (and thus memory hot-unplug).
The linux kernel has been supporting these since 4.11. All recent
enough guests are thus capable of handling the removal of a memory
device at all time, including during early boot.
Lift the limitation for the latest machine type. This means that
trying to unplug memory from a guest that doesn't support it will
likely just do nothing and the memory will only get removed at
next reboot. Such older guests can still get the existing behavior
by using an older machine type.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <160794035064.23292.17560963281911312439.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 6 +++++-
hw/ppc/spapr_events.c | 3 ++-
include/hw/ppc/spapr.h | 1 +
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 68a3ceb927..9f89b1c298 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -4069,7 +4069,8 @@ static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
- if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
+ if (!smc->pre_6_0_memory_unplug ||
+ spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
spapr_memory_unplug_request(hotplug_dev, dev, errp);
} else {
/* NOTE: this means there is a window after guest reset, prior to
@@ -4555,8 +4556,11 @@ DEFINE_SPAPR_MACHINE(6_0, "6.0", true);
*/
static void spapr_machine_5_2_class_options(MachineClass *mc)
{
+ SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
+
spapr_machine_6_0_class_options(mc);
compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
+ smc->pre_6_0_memory_unplug = true;
}
DEFINE_SPAPR_MACHINE(5_2, "5.2", false);
diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
index 3f37b49fd8..6aedd988b3 100644
--- a/hw/ppc/spapr_events.c
+++ b/hw/ppc/spapr_events.c
@@ -658,7 +658,8 @@ static void spapr_hotplug_req_event(uint8_t hp_id, uint8_t hp_action,
/* we should not be using count_indexed value unless the guest
* supports dedicated hotplug event source
*/
- g_assert(spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT));
+ g_assert(!SPAPR_MACHINE_GET_CLASS(spapr)->pre_6_0_memory_unplug ||
+ spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT));
hp->drc_id.count_indexed.count =
cpu_to_be32(drc_id->count_indexed.count);
hp->drc_id.count_indexed.index =
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index e0f10f252c..06a5b4259f 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -139,6 +139,7 @@ struct SpaprMachineClass {
hwaddr rma_limit; /* clamp the RMA to this size */
bool pre_5_1_assoc_refpoints;
bool pre_5_2_numa_associativity;
+ bool pre_6_0_memory_unplug;
bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
uint64_t *buid, hwaddr *pio,
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 09/22] spapr: Fix buffer overflow in spapr_numa_associativity_init()
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (7 preceding siblings ...)
2021-01-06 3:38 ` [PULL 08/22] spapr: Allow memory unplug to always succeed David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 10/22] spapr: Call spapr_drc_reset() for all DRCs at CAS David Gibson
` (14 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug
Cc: danielhb413, qemu-devel, Min Deng, qemu-ppc, David Gibson
From: Greg Kurz <groug@kaod.org>
Running a guest with 128 NUMA nodes crashes QEMU:
../../util/error.c:59: error_setv: Assertion `*errp == NULL' failed.
The crash happens when setting the FWNMI migration blocker:
2861 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) {
2862 /* Create the error string for live migration blocker */
2863 error_setg(&spapr->fwnmi_migration_blocker,
2864 "A machine check is being handled during migration. The handler"
2865 "may run and log hardware error on the destination");
2866 }
Inspection reveals that papr->fwnmi_migration_blocker isn't NULL:
(gdb) p spapr->fwnmi_migration_blocker
$1 = (Error *) 0x8000000004000000
Since this is the only place where papr->fwnmi_migration_blocker is
set, this means someone wrote there in our back. Further analysis
points to spapr_numa_associativity_init(), especially the part
that initializes the associative arrays for NVLink GPUs:
max_nodes_with_gpus = nb_numa_nodes + NVGPU_MAX_NUM;
ie. max_nodes_with_gpus = 128 + 6, but the array isn't sized to
accommodate the 6 extra nodes:
struct SpaprMachineState {
.
.
.
uint32_t numa_assoc_array[MAX_NODES][NUMA_ASSOC_SIZE];
Error *fwnmi_migration_blocker;
};
and the following loops happily overwrite spapr->fwnmi_migration_blocker,
and probably more:
for (i = nb_numa_nodes; i < max_nodes_with_gpus; i++) {
spapr->numa_assoc_array[i][0] = cpu_to_be32(MAX_DISTANCE_REF_POINTS);
for (j = 1; j < MAX_DISTANCE_REF_POINTS; j++) {
uint32_t gpu_assoc = smc->pre_5_1_assoc_refpoints ?
SPAPR_GPU_NUMA_ID : cpu_to_be32(i);
spapr->numa_assoc_array[i][j] = gpu_assoc;
}
spapr->numa_assoc_array[i][MAX_DISTANCE_REF_POINTS] = cpu_to_be32(i);
}
Fix the size of the array. This requires "hw/ppc/spapr.h" to see
NVGPU_MAX_NUM. Including "hw/pci-host/spapr.h" introduces a
circular dependency that breaks the build, so this moves the
definition of NVGPU_MAX_NUM to "hw/ppc/spapr.h" instead.
Reported-by: Min Deng <mdeng@redhat.com>
BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1908693
Fixes: dd7e1d7ae431 ("spapr_numa: move NVLink2 associativity handling to spapr_numa.c")
Cc: danielhb413@gmail.com
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <160829960428.734871.12634150161215429514.stgit@bahia.lan>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
include/hw/pci-host/spapr.h | 2 --
include/hw/ppc/spapr.h | 5 ++++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
index 4f58f0223b..bd014823a9 100644
--- a/include/hw/pci-host/spapr.h
+++ b/include/hw/pci-host/spapr.h
@@ -115,8 +115,6 @@ struct SpaprPhbState {
#define SPAPR_PCI_NV2RAM64_WIN_BASE SPAPR_PCI_LIMIT
#define SPAPR_PCI_NV2RAM64_WIN_SIZE (2 * TiB) /* For up to 6 GPUs 256GB each */
-/* Max number of these GPUsper a physical box */
-#define NVGPU_MAX_NUM 6
/* Max number of NVLinks per GPU in any physical box */
#define NVGPU_MAX_LINKS 3
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 06a5b4259f..1cc19575f5 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -112,6 +112,9 @@ typedef enum {
#define NUMA_ASSOC_SIZE (MAX_DISTANCE_REF_POINTS + 1)
#define VCPU_ASSOC_SIZE (NUMA_ASSOC_SIZE + 1)
+/* Max number of these GPUsper a physical box */
+#define NVGPU_MAX_NUM 6
+
typedef struct SpaprCapabilities SpaprCapabilities;
struct SpaprCapabilities {
uint8_t caps[SPAPR_CAP_NUM];
@@ -240,7 +243,7 @@ struct SpaprMachineState {
unsigned gpu_numa_id;
SpaprTpmProxy *tpm_proxy;
- uint32_t numa_assoc_array[MAX_NODES][NUMA_ASSOC_SIZE];
+ uint32_t numa_assoc_array[MAX_NODES + NVGPU_MAX_NUM][NUMA_ASSOC_SIZE];
Error *fwnmi_migration_blocker;
};
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 10/22] spapr: Call spapr_drc_reset() for all DRCs at CAS
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (8 preceding siblings ...)
2021-01-06 3:38 ` [PULL 09/22] spapr: Fix buffer overflow in spapr_numa_associativity_init() David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 11/22] spapr: Fix reset of transient DR connectors David Gibson
` (13 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug
Cc: Daniel Henrique Barboza, qemu-ppc, qemu-devel, David Gibson
From: Greg Kurz <groug@kaod.org>
Non-transient DRCs are either in the empty or the ready state,
which means spapr_drc_reset() doesn't change their state. It
is thus not needed to do any checking. Call spapr_drc_reset()
unconditionally and squash spapr_drc_transient() into its
only user, spapr_drc_needed().
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <20201218103400.689660-2-groug@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_drc.c | 8 ++------
hw/ppc/spapr_hcall.c | 7 ++++---
include/hw/ppc/spapr_drc.h | 3 ---
3 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index fc7e321fcd..8d62f55066 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -462,8 +462,9 @@ static const VMStateDescription vmstate_spapr_drc_unplug_requested = {
}
};
-bool spapr_drc_transient(SpaprDrc *drc)
+static bool spapr_drc_needed(void *opaque)
{
+ SpaprDrc *drc = opaque;
SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
/*
@@ -483,11 +484,6 @@ bool spapr_drc_transient(SpaprDrc *drc)
spapr_drc_unplug_requested(drc);
}
-static bool spapr_drc_needed(void *opaque)
-{
- return spapr_drc_transient(opaque);
-}
-
static const VMStateDescription vmstate_spapr_drc = {
.name = "spapr_drc",
.version_id = 1,
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index c0ea0bd579..4e9d50c254 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1650,9 +1650,10 @@ static void spapr_handle_transient_dev_before_cas(SpaprMachineState *spapr)
prop->name,
&error_abort));
- if (spapr_drc_transient(drc)) {
- spapr_drc_reset(drc);
- }
+ /*
+ * This will complete any pending plug/unplug requests.
+ */
+ spapr_drc_reset(drc);
}
spapr_clear_pending_hotplug_events(spapr);
diff --git a/include/hw/ppc/spapr_drc.h b/include/hw/ppc/spapr_drc.h
index def3593adc..cff5e707d0 100644
--- a/include/hw/ppc/spapr_drc.h
+++ b/include/hw/ppc/spapr_drc.h
@@ -244,9 +244,6 @@ int spapr_dt_drc(void *fdt, int offset, Object *owner, uint32_t drc_type_mask);
void spapr_drc_attach(SpaprDrc *drc, DeviceState *d);
void spapr_drc_detach(SpaprDrc *drc);
-/* Returns true if a hot plug/unplug request is pending */
-bool spapr_drc_transient(SpaprDrc *drc);
-
static inline bool spapr_drc_unplug_requested(SpaprDrc *drc)
{
return drc->unplug_requested;
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 11/22] spapr: Fix reset of transient DR connectors
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (9 preceding siblings ...)
2021-01-06 3:38 ` [PULL 10/22] spapr: Call spapr_drc_reset() for all DRCs at CAS David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 12/22] spapr: Introduce spapr_drc_reset_all() David Gibson
` (12 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug
Cc: Daniel Henrique Barboza, qemu-ppc, qemu-devel, David Gibson
From: Greg Kurz <groug@kaod.org>
Documentation of object_property_iter_init() clearly stipulates that
"it is forbidden to modify the property list while iterating". But this
is exactly what we do when resetting transient DR connectors during CAS.
The call to spapr_drc_reset() can finalize the hot-unplug sequence of a
PHB or a PCI bridge, both of which will then in turn destroy their PCI
DRCs. This could potentially invalidate the iterator. It is pure luck
that this haven't caused any issues so far.
Change spapr_drc_reset() to return true if it caused a device to be
removed. Restart from scratch in this case. This can potentially
increase the overall DRC reset time, especially with a high maxmem
which generates a lot of LMB DRCs. But this kind of setup is rare,
and so is the use case of rebooting a guest while doing hot-unplug.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <20201218103400.689660-3-groug@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_drc.c | 6 +++++-
hw/ppc/spapr_hcall.c | 8 +++++++-
include/hw/ppc/spapr_drc.h | 3 ++-
3 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index 8d62f55066..5b5e2ac58a 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -417,9 +417,10 @@ void spapr_drc_detach(SpaprDrc *drc)
spapr_drc_release(drc);
}
-void spapr_drc_reset(SpaprDrc *drc)
+bool spapr_drc_reset(SpaprDrc *drc)
{
SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
+ bool unplug_completed = false;
trace_spapr_drc_reset(spapr_drc_index(drc));
@@ -428,6 +429,7 @@ void spapr_drc_reset(SpaprDrc *drc)
*/
if (drc->unplug_requested) {
spapr_drc_release(drc);
+ unplug_completed = true;
}
if (drc->dev) {
@@ -444,6 +446,8 @@ void spapr_drc_reset(SpaprDrc *drc)
drc->ccs_offset = -1;
drc->ccs_depth = -1;
}
+
+ return unplug_completed;
}
static bool spapr_drc_unplug_requested_needed(void *opaque)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 4e9d50c254..aa22830ac4 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1639,6 +1639,7 @@ static void spapr_handle_transient_dev_before_cas(SpaprMachineState *spapr)
ObjectPropertyIterator iter;
drc_container = container_get(object_get_root(), "/dr-connector");
+restart:
object_property_iter_init(&iter, drc_container);
while ((prop = object_property_iter_next(&iter))) {
SpaprDrc *drc;
@@ -1652,8 +1653,13 @@ static void spapr_handle_transient_dev_before_cas(SpaprMachineState *spapr)
/*
* This will complete any pending plug/unplug requests.
+ * In case of a unplugged PHB or PCI bridge, this will
+ * cause some DRCs to be destroyed and thus potentially
+ * invalidate the iterator.
*/
- spapr_drc_reset(drc);
+ if (spapr_drc_reset(drc)) {
+ goto restart;
+ }
}
spapr_clear_pending_hotplug_events(spapr);
diff --git a/include/hw/ppc/spapr_drc.h b/include/hw/ppc/spapr_drc.h
index cff5e707d0..5d80019f82 100644
--- a/include/hw/ppc/spapr_drc.h
+++ b/include/hw/ppc/spapr_drc.h
@@ -224,7 +224,8 @@ static inline bool spapr_drc_hotplugged(DeviceState *dev)
return dev->hotplugged && !runstate_check(RUN_STATE_INMIGRATE);
}
-void spapr_drc_reset(SpaprDrc *drc);
+/* Returns true if an unplug request completed */
+bool spapr_drc_reset(SpaprDrc *drc);
uint32_t spapr_drc_index(SpaprDrc *drc);
SpaprDrcType spapr_drc_type(SpaprDrc *drc);
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 12/22] spapr: Introduce spapr_drc_reset_all()
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (10 preceding siblings ...)
2021-01-06 3:38 ` [PULL 11/22] spapr: Fix reset of transient DR connectors David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 13/22] spapr: Use spapr_drc_reset_all() at machine reset David Gibson
` (11 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug
Cc: Daniel Henrique Barboza, qemu-ppc, qemu-devel, David Gibson
From: Greg Kurz <groug@kaod.org>
No need to expose the way DRCs are traversed outside of spapr_drc.c.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <20201218103400.689660-4-groug@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_drc.c | 31 +++++++++++++++++++++++++++++
hw/ppc/spapr_hcall.c | 40 ++++++--------------------------------
include/hw/ppc/spapr_drc.h | 6 ++++++
3 files changed, 43 insertions(+), 34 deletions(-)
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index 5b5e2ac58a..a4d2608017 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -949,6 +949,37 @@ out:
return ret;
}
+void spapr_drc_reset_all(SpaprMachineState *spapr)
+{
+ Object *drc_container;
+ ObjectProperty *prop;
+ ObjectPropertyIterator iter;
+
+ drc_container = container_get(object_get_root(), DRC_CONTAINER_PATH);
+restart:
+ object_property_iter_init(&iter, drc_container);
+ while ((prop = object_property_iter_next(&iter))) {
+ SpaprDrc *drc;
+
+ if (!strstart(prop->type, "link<", NULL)) {
+ continue;
+ }
+ drc = SPAPR_DR_CONNECTOR(object_property_get_link(drc_container,
+ prop->name,
+ &error_abort));
+
+ /*
+ * This will complete any pending plug/unplug requests.
+ * In case of a unplugged PHB or PCI bridge, this will
+ * cause some DRCs to be destroyed and thus potentially
+ * invalidate the iterator.
+ */
+ if (spapr_drc_reset(drc)) {
+ goto restart;
+ }
+ }
+}
+
/*
* RTAS calls
*/
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index aa22830ac4..e5dfc1ba7a 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1632,39 +1632,6 @@ static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat,
return best_compat;
}
-static void spapr_handle_transient_dev_before_cas(SpaprMachineState *spapr)
-{
- Object *drc_container;
- ObjectProperty *prop;
- ObjectPropertyIterator iter;
-
- drc_container = container_get(object_get_root(), "/dr-connector");
-restart:
- object_property_iter_init(&iter, drc_container);
- while ((prop = object_property_iter_next(&iter))) {
- SpaprDrc *drc;
-
- if (!strstart(prop->type, "link<", NULL)) {
- continue;
- }
- drc = SPAPR_DR_CONNECTOR(object_property_get_link(drc_container,
- prop->name,
- &error_abort));
-
- /*
- * This will complete any pending plug/unplug requests.
- * In case of a unplugged PHB or PCI bridge, this will
- * cause some DRCs to be destroyed and thus potentially
- * invalidate the iterator.
- */
- if (spapr_drc_reset(drc)) {
- goto restart;
- }
- }
-
- spapr_clear_pending_hotplug_events(spapr);
-}
-
target_ulong do_client_architecture_support(PowerPCCPU *cpu,
SpaprMachineState *spapr,
target_ulong vec,
@@ -1822,7 +1789,12 @@ target_ulong do_client_architecture_support(PowerPCCPU *cpu,
spapr_irq_update_active_intc(spapr);
- spapr_handle_transient_dev_before_cas(spapr);
+ /*
+ * Process all pending hot-plug/unplug requests now. An updated full
+ * rendered FDT will be returned to the guest.
+ */
+ spapr_drc_reset_all(spapr);
+ spapr_clear_pending_hotplug_events(spapr);
/*
* If spapr_machine_reset() did not set up a HPT but one is necessary
diff --git a/include/hw/ppc/spapr_drc.h b/include/hw/ppc/spapr_drc.h
index 5d80019f82..8982927d5c 100644
--- a/include/hw/ppc/spapr_drc.h
+++ b/include/hw/ppc/spapr_drc.h
@@ -245,6 +245,12 @@ int spapr_dt_drc(void *fdt, int offset, Object *owner, uint32_t drc_type_mask);
void spapr_drc_attach(SpaprDrc *drc, DeviceState *d);
void spapr_drc_detach(SpaprDrc *drc);
+/*
+ * Reset all DRCs, causing pending hot-plug/unplug requests to complete.
+ * Safely handles potential DRC removal (eg. PHBs or PCI bridges).
+ */
+void spapr_drc_reset_all(struct SpaprMachineState *spapr);
+
static inline bool spapr_drc_unplug_requested(SpaprDrc *drc)
{
return drc->unplug_requested;
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 13/22] spapr: Use spapr_drc_reset_all() at machine reset
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (11 preceding siblings ...)
2021-01-06 3:38 ` [PULL 12/22] spapr: Introduce spapr_drc_reset_all() David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 14/22] spapr: Add drc_ prefix to the DRC realize and unrealize functions David Gibson
` (10 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug
Cc: Daniel Henrique Barboza, qemu-ppc, qemu-devel, David Gibson
From: Greg Kurz <groug@kaod.org>
Documentation of object_child_foreach_recursive() clearly stipulates
that "it is forbidden to add or remove children from @obj from the @fn
callback". But this is exactly what we do during machine reset. The call
to spapr_drc_reset() can finalize the hot-unplug sequence of a PHB or a
PCI bridge, both of which will then in turn destroy their PCI DRCs. This
could potentially invalidate the iterator used by do_object_child_foreach().
It is pure luck that this haven't caused any issues so far.
Use spapr_drc_reset_all() since it can cope with DRC removal.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <20201218103400.689660-5-groug@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 15 +--------------
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 9f89b1c298..2c403b574e 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1566,19 +1566,6 @@ void spapr_setup_hpt(SpaprMachineState *spapr)
}
}
-static int spapr_reset_drcs(Object *child, void *opaque)
-{
- SpaprDrc *drc =
- (SpaprDrc *) object_dynamic_cast(child,
- TYPE_SPAPR_DR_CONNECTOR);
-
- if (drc) {
- spapr_drc_reset(drc);
- }
-
- return 0;
-}
-
static void spapr_machine_reset(MachineState *machine)
{
SpaprMachineState *spapr = SPAPR_MACHINE(machine);
@@ -1633,7 +1620,7 @@ static void spapr_machine_reset(MachineState *machine)
* will crash QEMU if the DIMM holding the vring goes away). To avoid such
* situations, we reset DRCs after all devices have been reset.
*/
- object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
+ spapr_drc_reset_all(spapr);
spapr_clear_pending_events(spapr);
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 14/22] spapr: Add drc_ prefix to the DRC realize and unrealize functions
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (12 preceding siblings ...)
2021-01-06 3:38 ` [PULL 13/22] spapr: Use spapr_drc_reset_all() at machine reset David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 15/22] ppc: Fix build with --without-default-devices David Gibson
` (9 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug
Cc: Daniel Henrique Barboza, qemu-ppc, qemu-devel, David Gibson
From: Greg Kurz <groug@kaod.org>
Use a less generic name for an easier experience with tools such as
cscope or grep.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <20201218103400.689660-6-groug@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_drc.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index a4d2608017..8571d5bafe 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -503,7 +503,7 @@ static const VMStateDescription vmstate_spapr_drc = {
}
};
-static void realize(DeviceState *d, Error **errp)
+static void drc_realize(DeviceState *d, Error **errp)
{
SpaprDrc *drc = SPAPR_DR_CONNECTOR(d);
Object *root_container;
@@ -530,7 +530,7 @@ static void realize(DeviceState *d, Error **errp)
trace_spapr_drc_realize_complete(spapr_drc_index(drc));
}
-static void unrealize(DeviceState *d)
+static void drc_unrealize(DeviceState *d)
{
SpaprDrc *drc = SPAPR_DR_CONNECTOR(d);
Object *root_container;
@@ -579,8 +579,8 @@ static void spapr_dr_connector_class_init(ObjectClass *k, void *data)
{
DeviceClass *dk = DEVICE_CLASS(k);
- dk->realize = realize;
- dk->unrealize = unrealize;
+ dk->realize = drc_realize;
+ dk->unrealize = drc_unrealize;
/*
* Reason: DR connector needs to be wired to either the machine or to a
* PHB in spapr_dr_connector_new().
@@ -628,7 +628,7 @@ static void realize_physical(DeviceState *d, Error **errp)
SpaprDrcPhysical *drcp = SPAPR_DRC_PHYSICAL(d);
Error *local_err = NULL;
- realize(d, &local_err);
+ drc_realize(d, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@@ -644,7 +644,7 @@ static void unrealize_physical(DeviceState *d)
{
SpaprDrcPhysical *drcp = SPAPR_DRC_PHYSICAL(d);
- unrealize(d);
+ drc_unrealize(d);
vmstate_unregister(VMSTATE_IF(drcp), &vmstate_spapr_drc_physical, drcp);
qemu_unregister_reset(drc_physical_reset, drcp);
}
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 15/22] ppc: Fix build with --without-default-devices
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (13 preceding siblings ...)
2021-01-06 3:38 ` [PULL 14/22] spapr: Add drc_ prefix to the DRC realize and unrealize functions David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 16/22] ppc: Simplify reverse dependencies of POWERNV and PSERIES on XICS and XIVE David Gibson
` (8 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug; +Cc: David Gibson, qemu-ppc, qemu-devel
From: Greg Kurz <groug@kaod.org>
Linking of the qemu-system-ppc64 fails on a POWER9 host when
--without-default-devices is passed to configure:
$ ./configure --without-default-devices \
--target-list=ppc64-softmmu && make
...
libqemu-ppc64-softmmu.fa.p/hw_ppc_e500.c.o: In function `ppce500_init_mpic_kvm':
/home/greg/Work/qemu/qemu-ppc/build/../hw/ppc/e500.c:777: undefined reference to `kvm_openpic_connect_vcpu'
libqemu-ppc64-softmmu.fa.p/hw_ppc_spapr_irq.c.o: In function `spapr_irq_check':
/home/greg/Work/qemu/qemu-ppc/build/../hw/ppc/spapr_irq.c:189: undefined reference to `xics_kvm_has_broken_disconnect'
libqemu-ppc64-softmmu.fa.p/hw_intc_spapr_xive.c.o: In function `spapr_xive_post_load':
/home/greg/Work/qemu/qemu-ppc/build/../hw/intc/spapr_xive.c:530: undefined reference to `kvmppc_xive_post_load'
... and tons of other symbols belonging to the KVM backend of the
openpic, XICS and XIVE interrupt controllers.
It turns out that OPENPIC_KVM, XICS_KVM and XIVE_KVM are marked
to depend on KVM but this has no effect when minikconf runs in
allnoconfig mode. Such reverse dependencies should rather be
handled with a 'select' statement, eg.
config OPENPIC
select OPENPIC_KVM if KVM
or even better by getting rid of the intermediate _KVM config
and directly checking CONFIG_KVM in the meson.build file:
specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_OPENPIC'],
if_true: files('openpic_kvm.c'))
Go for the latter with OPENPIC, XICS and XIVE.
This went unnoticed so far because CI doesn't test the build with
--without-default-devices and KVM enabled on a POWER host.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <160883056791.253005.14924294027763955653.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/Kconfig | 10 ----------
hw/intc/meson.build | 9 ++++++---
hw/ppc/Kconfig | 5 -----
3 files changed, 6 insertions(+), 18 deletions(-)
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 468d548ca7..fa2695e58d 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -30,11 +30,6 @@ config ARM_GIC_KVM
default y
depends on ARM_GIC && KVM
-config OPENPIC_KVM
- bool
- default y
- depends on OPENPIC && KVM
-
config XICS
bool
depends on POWERNV || PSERIES
@@ -43,11 +38,6 @@ config XICS_SPAPR
bool
select XICS
-config XICS_KVM
- bool
- default y
- depends on XICS && KVM
-
config ALLWINNER_A10_PIC
bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 68da782ad2..b6c9218908 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -39,7 +39,8 @@ specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_lioint
specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c'))
specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_intc.c'))
specific_ss.add(when: 'CONFIG_OMPIC', if_true: files('ompic.c'))
-specific_ss.add(when: 'CONFIG_OPENPIC_KVM', if_true: files('openpic_kvm.c'))
+specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_OPENPIC'],
+ if_true: files('openpic_kvm.c'))
specific_ss.add(when: 'CONFIG_POWERNV', if_true: files('xics_pnv.c', 'pnv_xive.c'))
specific_ss.add(when: 'CONFIG_PPC_UIC', if_true: files('ppc-uic.c'))
specific_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_ic.c', 'bcm2836_control.c'))
@@ -50,8 +51,10 @@ specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
-specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
+specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'],
+ if_true: files('xics_kvm.c'))
specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c'))
-specific_ss.add(when: 'CONFIG_XIVE_KVM', if_true: files('spapr_xive_kvm.c'))
+specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
+ if_true: files('spapr_xive_kvm.c'))
specific_ss.add(when: 'CONFIG_XIVE_SPAPR', if_true: files('spapr_xive.c'))
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 982d55f587..e35710c7c3 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -139,11 +139,6 @@ config XIVE_SPAPR
depends on PSERIES
select XIVE
-config XIVE_KVM
- bool
- default y
- depends on XIVE_SPAPR && KVM
-
# Only used by 64-bit targets
config FW_CFG_PPC
bool
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 16/22] ppc: Simplify reverse dependencies of POWERNV and PSERIES on XICS and XIVE
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (14 preceding siblings ...)
2021-01-06 3:38 ` [PULL 15/22] ppc: Fix build with --without-default-devices David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 17/22] pnv: Fix reverse dependency on PCI express root ports David Gibson
` (7 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug; +Cc: David Gibson, qemu-ppc, qemu-devel
From: Greg Kurz <groug@kaod.org>
Have PSERIES to select XICS and XIVE, and directly check PSERIES
in hw/intc/meson.build to enable build of the XICS and XIVE sPAPR
backends, like POWERNV already does. This allows to get rid of the
intermediate XICS_SPAPR and XIVE_SPAPR.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <160883057560.253005.4206568349917633920.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/Kconfig | 4 +---
hw/intc/meson.build | 3 +--
hw/ppc/Kconfig | 14 ++------------
3 files changed, 4 insertions(+), 17 deletions(-)
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index fa2695e58d..c18d11142a 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -32,11 +32,9 @@ config ARM_GIC_KVM
config XICS
bool
- depends on POWERNV || PSERIES
-config XICS_SPAPR
+config XIVE
bool
- select XICS
config ALLWINNER_A10_PIC
bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index b6c9218908..53cba11569 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -53,8 +53,7 @@ specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'],
if_true: files('xics_kvm.c'))
-specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
+specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('xics_spapr.c', 'spapr_xive.c'))
specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c'))
specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
if_true: files('spapr_xive_kvm.c'))
-specific_ss.add(when: 'CONFIG_XIVE_SPAPR', if_true: files('spapr_xive.c'))
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index e35710c7c3..a213994ebf 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -7,8 +7,8 @@ config PSERIES
select PCI
select SPAPR_VSCSI
select VFIO if LINUX # needed by spapr_pci_vfio.c
- select XICS_SPAPR
- select XIVE_SPAPR
+ select XICS
+ select XIVE
select MSI_NONBROKEN
select FDT_PPC
select CHRP_NVRAM
@@ -129,16 +129,6 @@ config VIRTEX
select XILINX_ETHLITE
select FDT_PPC
-config XIVE
- bool
- depends on POWERNV || PSERIES
-
-config XIVE_SPAPR
- bool
- default y
- depends on PSERIES
- select XIVE
-
# Only used by 64-bit targets
config FW_CFG_PPC
bool
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 17/22] pnv: Fix reverse dependency on PCI express root ports
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (15 preceding siblings ...)
2021-01-06 3:38 ` [PULL 16/22] ppc: Simplify reverse dependencies of POWERNV and PSERIES on XICS and XIVE David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 18/22] ppc4xx: Move common dependency on serial to common option David Gibson
` (6 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug
Cc: Cédric Le Goater, David Gibson, qemu-ppc, qemu-devel
From: Greg Kurz <groug@kaod.org>
qemu-system-ppc64 built with --without-default-devices crashes:
Type 'pnv-phb4-root-port' is missing its parent 'pcie-root-port-base'
Aborted (core dumped)
Have POWERNV to select PCIE_PORT. This is done through a
new PCI_POWERNV config in hw/pci-host/Kconfig since POWERNV
doesn't have a direct dependency on PCI. For this reason,
PCI_EXPRESS and MSI_NONBROKEN are also moved under
PCI_POWERNV.
Signed-off-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <160883058299.253005.342913177952681375.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/Kconfig | 5 +++++
hw/pci-host/meson.build | 2 +-
hw/ppc/Kconfig | 3 +--
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 036a61877a..eb03f0489d 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -60,3 +60,8 @@ config PCI_BONITO
select PCI
select UNIMP
bool
+
+config PCI_POWERNV
+ select PCI_EXPRESS
+ select MSI_NONBROKEN
+ select PCIE_PORT
diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build
index e6d1b89684..da9d1a9964 100644
--- a/hw/pci-host/meson.build
+++ b/hw/pci-host/meson.build
@@ -23,7 +23,7 @@ pci_ss.add(when: 'CONFIG_VERSATILE_PCI', if_true: files('versatile.c'))
softmmu_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss)
-specific_ss.add(when: 'CONFIG_POWERNV', if_true: files(
+specific_ss.add(when: 'CONFIG_PCI_POWERNV', if_true: files(
'pnv_phb3.c',
'pnv_phb3_msi.c',
'pnv_phb3_pbcq.c',
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index a213994ebf..d11dc30509 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -29,8 +29,7 @@ config POWERNV
select XICS
select XIVE
select FDT_PPC
- select PCI_EXPRESS
- select MSI_NONBROKEN
+ select PCI_POWERNV
config PPC405
bool
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 18/22] ppc4xx: Move common dependency on serial to common option
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (16 preceding siblings ...)
2021-01-06 3:38 ` [PULL 17/22] pnv: Fix reverse dependency on PCI express root ports David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 19/22] sam460ex: Remove FDT_PPC dependency from KConfig David Gibson
` (5 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug; +Cc: David Gibson, qemu-ppc, qemu-devel
From: BALATON Zoltan via <qemu-ppc@nongnu.org>
All machines that select SERIAL also select PPC4XX so we can just add
this common dependency there once.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <94f1eb7cfb7f315bd883d825f3ce7e0cfc2f2b69.1609636173.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/Kconfig | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index d11dc30509..d2329edbab 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -36,7 +36,6 @@ config PPC405
select M48T59
select PFLASH_CFI02
select PPC4XX
- select SERIAL
config PPC440
bool
@@ -45,7 +44,6 @@ config PPC440
imply E1000_PCI
select PCI_EXPRESS
select PPC4XX
- select SERIAL
select FDT_PPC
config PPC4XX
@@ -53,6 +51,7 @@ config PPC4XX
select BITBANG_I2C
select PCI
select PPC_UIC
+ select SERIAL
config SAM460EX
bool
@@ -61,7 +60,6 @@ config SAM460EX
select IDE_SII3112
select M41T80
select PPC440
- select SERIAL
select SM501
select SMBUS_EEPROM
select USB_EHCI_SYSBUS
@@ -123,7 +121,6 @@ config VIRTEX
bool
select PPC4XX
select PFLASH_CFI01
- select SERIAL
select XILINX
select XILINX_ETHLITE
select FDT_PPC
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 19/22] sam460ex: Remove FDT_PPC dependency from KConfig
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (17 preceding siblings ...)
2021-01-06 3:38 ` [PULL 18/22] ppc4xx: Move common dependency on serial to common option David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 20/22] ppc440_pcix: Improve comment for IRQ mapping David Gibson
` (4 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug
Cc: Philippe Mathieu-Daudé, qemu-ppc, qemu-devel, David Gibson
From: BALATON Zoltan via <qemu-ppc@nongnu.org>
Dependency on FDT_PPC was added in commit b0048f76095
("hw/ppc/Kconfig: Only select FDT helper for machines using it") but
it does not seem to be really necessary so remove it again.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <7461a20b129a912aeacdb9ad115a55f0b84c8726.1609636173.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index d2329edbab..7e267d94a1 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -64,7 +64,6 @@ config SAM460EX
select SMBUS_EEPROM
select USB_EHCI_SYSBUS
select USB_OHCI
- select FDT_PPC
config PREP
bool
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 20/22] ppc440_pcix: Improve comment for IRQ mapping
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (18 preceding siblings ...)
2021-01-06 3:38 ` [PULL 19/22] sam460ex: Remove FDT_PPC dependency from KConfig David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 21/22] ppc440_pcix: Fix register write trace event David Gibson
` (3 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug; +Cc: David Gibson, qemu-ppc, qemu-devel
From: BALATON Zoltan via <qemu-ppc@nongnu.org>
The code mapping all PCI interrupts to a single CPU IRQ works but is
not trivial so document it in a comment.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <c25c0310510672b58466e795fd701e65e8f1ff97.1609636173.git.balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc440_pcix.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c
index ee952314c8..eb1290ffc8 100644
--- a/hw/ppc/ppc440_pcix.c
+++ b/hw/ppc/ppc440_pcix.c
@@ -415,8 +415,15 @@ static void ppc440_pcix_reset(DeviceState *dev)
s->sts = 0;
}
-/* All pins from each slot are tied to a single board IRQ.
- * This may need further refactoring for other boards. */
+/*
+ * All four IRQ[ABCD] pins from all slots are tied to a single board
+ * IRQ, so our mapping function here maps everything to IRQ 0.
+ * The code in pci_change_irq_level() tracks the number of times
+ * the mapped IRQ is asserted and deasserted, so if multiple devices
+ * assert an IRQ at the same time the behaviour is correct.
+ *
+ * This may need further refactoring for boards that use multiple IRQ lines.
+ */
static int ppc440_pcix_map_irq(PCIDevice *pci_dev, int irq_num)
{
trace_ppc440_pcix_map_irq(pci_dev->devfn, irq_num, 0);
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 21/22] ppc440_pcix: Fix register write trace event
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (19 preceding siblings ...)
2021-01-06 3:38 ` [PULL 20/22] ppc440_pcix: Improve comment for IRQ mapping David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 3:38 ` [PULL 22/22] ppc440_pcix: Fix up pci config access David Gibson
` (2 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug
Cc: Philippe Mathieu-Daudé, qemu-ppc, qemu-devel, David Gibson
From: BALATON Zoltan via <qemu-ppc@nongnu.org>
The trace event for pci_host_config_write() was also using the trace
event for read. Add corresponding trace and correct this.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <a6c7dcf7153cc537123ed8ceac060f2f64a883cb.1609636173.git.balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc440_pcix.c | 2 +-
hw/ppc/trace-events | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c
index eb1290ffc8..7829d3e556 100644
--- a/hw/ppc/ppc440_pcix.c
+++ b/hw/ppc/ppc440_pcix.c
@@ -169,7 +169,7 @@ static void ppc440_pcix_reg_write4(void *opaque, hwaddr addr,
{
struct PPC440PCIXState *s = opaque;
- trace_ppc440_pcix_reg_read(addr, val);
+ trace_ppc440_pcix_reg_write(addr, val, size);
switch (addr) {
case PCI_VENDOR_ID ... PCI_MAX_LAT:
stl_le_p(s->dev->config + addr, val);
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 6d8d095aa2..1e91984526 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -96,3 +96,4 @@ ppc440_pcix_set_irq(int irq_num) "PCI irq %d"
ppc440_pcix_update_pim(int idx, uint64_t size, uint64_t la) "Added window %d of size=0x%" PRIx64 " to CPU=0x%" PRIx64
ppc440_pcix_update_pom(int idx, uint32_t size, uint64_t la, uint64_t pcia) "Added window %d of size=0x%x from CPU=0x%" PRIx64 " to PCI=0x%" PRIx64
ppc440_pcix_reg_read(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32
+ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size) "addr 0x%" PRIx64 " = 0x%" PRIx32 " size 0x%" PRIx32
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PULL 22/22] ppc440_pcix: Fix up pci config access
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (20 preceding siblings ...)
2021-01-06 3:38 ` [PULL 21/22] ppc440_pcix: Fix register write trace event David Gibson
@ 2021-01-06 3:38 ` David Gibson
2021-01-06 6:12 ` [PULL 00/22] ppc-for-6.0 queue 20210106 BALATON Zoltan via
2021-01-06 13:30 ` Peter Maydell
23 siblings, 0 replies; 26+ messages in thread
From: David Gibson @ 2021-01-06 3:38 UTC (permalink / raw)
To: peter.maydell, groug; +Cc: David Gibson, qemu-ppc, qemu-devel
From: BALATON Zoltan via <qemu-ppc@nongnu.org>
This fixes a long standing issue with MorphOS booting on sam460ex
which turns out to be because of suspicious values written to PCI
config address that apparently works on real machine but caused wrong
access on this device model. This replaces a previous work around for
this with a better fix that makes it work.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <6fd215ab2bc5f8d4455cd20ed1a2f059e4415fe5.1609636173.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc440_pcix.c | 37 ++++++++++++++++++++++---------------
1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c
index 7829d3e556..91cbcd0504 100644
--- a/hw/ppc/ppc440_pcix.c
+++ b/hw/ppc/ppc440_pcix.c
@@ -449,28 +449,35 @@ static AddressSpace *ppc440_pcix_set_iommu(PCIBus *b, void *opaque, int devfn)
return &s->bm_as;
}
-/* The default pci_host_data_{read,write} functions in pci/pci_host.c
- * deny access to registers without bit 31 set but our clients want
- * this to work so we have to override these here */
-static void pci_host_data_write(void *opaque, hwaddr addr,
- uint64_t val, unsigned len)
+/*
+ * Some guests on sam460ex write all kinds of garbage here such as
+ * missing enable bit and low bits set and still expect this to work
+ * (apparently it does on real hardware because these boot there) so
+ * we have to override these ops here and fix it up
+ */
+static void pci_host_config_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned len)
{
PCIHostState *s = opaque;
- pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
+
+ if (addr != 0 || len != 4) {
+ return;
+ }
+ s->config_reg = (val & 0xfffffffcULL) | (1UL << 31);
}
-static uint64_t pci_host_data_read(void *opaque,
- hwaddr addr, unsigned len)
+static uint64_t pci_host_config_read(void *opaque, hwaddr addr,
+ unsigned len)
{
PCIHostState *s = opaque;
- uint32_t val;
- val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
+ uint32_t val = s->config_reg;
+
return val;
}
-const MemoryRegionOps ppc440_pcix_host_data_ops = {
- .read = pci_host_data_read,
- .write = pci_host_data_write,
+const MemoryRegionOps ppc440_pcix_host_conf_ops = {
+ .read = pci_host_config_read,
+ .write = pci_host_config_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
@@ -497,9 +504,9 @@ static void ppc440_pcix_realize(DeviceState *dev, Error **errp)
pci_setup_iommu(h->bus, ppc440_pcix_set_iommu, s);
memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
- memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops,
+ memory_region_init_io(&h->conf_mem, OBJECT(s), &ppc440_pcix_host_conf_ops,
h, "pci-conf-idx", 4);
- memory_region_init_io(&h->data_mem, OBJECT(s), &ppc440_pcix_host_data_ops,
+ memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops,
h, "pci-conf-data", 4);
memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
"pci.reg", PPC440_REG_SIZE);
--
2.29.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PULL 00/22] ppc-for-6.0 queue 20210106
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (21 preceding siblings ...)
2021-01-06 3:38 ` [PULL 22/22] ppc440_pcix: Fix up pci config access David Gibson
@ 2021-01-06 6:12 ` BALATON Zoltan via
2021-01-06 13:30 ` Peter Maydell
23 siblings, 0 replies; 26+ messages in thread
From: BALATON Zoltan via @ 2021-01-06 6:12 UTC (permalink / raw)
To: David Gibson; +Cc: peter.maydell, qemu-ppc, groug, qemu-devel
[-- Attachment #1: Type: TEXT/PLAIN, Size: 3897 bytes --]
On Wed, 6 Jan 2021, David Gibson wrote:
> The following changes since commit 52d25464605dc20022ad94aa8bc8e8473e600833:
>
> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210104' into staging (2021-01-05 16:18:20 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/dgibson/qemu.git tags/ppc-for-6.0-20210106
>
> for you to fetch changes up to 5cbd51a5a58098444ffa246ece2013849be04299:
>
> ppc440_pcix: Fix up pci config access (2021-01-06 11:09:59 +1100)
>
> ----------------------------------------------------------------
> ppc patch queue 2021-01-06
>
> First pull request for 2021, which has a bunch of things accumulated
> over the holidays. Includes:
> * A number of cleanups to sam460ex and ppc440 code from BALATON Zoltan
> * Several fixes for builds with --without-default-devices from Greg Kurz
> * Fixes for some DRC reset problems from Greg Kurz
> * QOM conversion of the PPC 4xx UIC devices from Peter Maydell
> * Some other assorted fixes and cleanups
>
> ----------------------------------------------------------------
> BALATON Zoltan via (5):
> ppc4xx: Move common dependency on serial to common option
> sam460ex: Remove FDT_PPC dependency from KConfig
I've sent a v4 without these pathces
> ppc440_pcix: Improve comment for IRQ mapping
> ppc440_pcix: Fix register write trace event
> ppc440_pcix: Fix up pci config access
but including another one missing from here so this pull request does not
have the latest set of patches. Of course it's difficult for me to tell
you when I can't send mail to your domain. We're trying to figure out why.
Regards,
BALATON Zoltan
> Cédric Le Goater (1):
> spapr/xive: Make spapr_xive_pic_print_info() static
>
> Greg Kurz (12):
> spapr: DRC lookup cannot fail
> spapr: Fix DR properties of the root node
> spapr: Allow memory unplug to always succeed
> spapr: Fix buffer overflow in spapr_numa_associativity_init()
> spapr: Call spapr_drc_reset() for all DRCs at CAS
> spapr: Fix reset of transient DR connectors
> spapr: Introduce spapr_drc_reset_all()
> spapr: Use spapr_drc_reset_all() at machine reset
> spapr: Add drc_ prefix to the DRC realize and unrealize functions
> ppc: Fix build with --without-default-devices
> ppc: Simplify reverse dependencies of POWERNV and PSERIES on XICS and XIVE
> pnv: Fix reverse dependency on PCI express root ports
>
> Peter Maydell (4):
> hw/ppc/ppc4xx_devs: Make code style fixes to UIC code
> ppc: Convert PPC UIC to a QOM device
> hw/ppc/virtex_ml507: Drop use of ppcuic_init()
> hw/ppc/ppc440_bamboo: Drop use of ppcuic_init()
>
> MAINTAINERS | 2 +
> hw/intc/Kconfig | 17 +--
> hw/intc/meson.build | 13 +-
> hw/intc/ppc-uic.c | 321 ++++++++++++++++++++++++++++++++++++++++++++
> hw/intc/spapr_xive.c | 2 +-
> hw/pci-host/Kconfig | 5 +
> hw/pci-host/meson.build | 2 +-
> hw/ppc/Kconfig | 29 +---
> hw/ppc/ppc440_bamboo.c | 38 ++++--
> hw/ppc/ppc440_pcix.c | 50 ++++---
> hw/ppc/ppc4xx_devs.c | 262 +++++-------------------------------
> hw/ppc/spapr.c | 44 +++---
> hw/ppc/spapr_drc.c | 63 +++++++--
> hw/ppc/spapr_events.c | 3 +-
> hw/ppc/spapr_hcall.c | 33 +----
> hw/ppc/trace-events | 1 +
> hw/ppc/virtex_ml507.c | 21 ++-
> include/hw/intc/ppc-uic.h | 73 ++++++++++
> include/hw/pci-host/spapr.h | 2 -
> include/hw/ppc/spapr.h | 6 +-
> include/hw/ppc/spapr_drc.h | 10 +-
> include/hw/ppc/spapr_xive.h | 2 -
> 22 files changed, 616 insertions(+), 383 deletions(-)
> create mode 100644 hw/intc/ppc-uic.c
> create mode 100644 include/hw/intc/ppc-uic.h
>
>
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PULL 00/22] ppc-for-6.0 queue 20210106
2021-01-06 3:37 [PULL 00/22] ppc-for-6.0 queue 20210106 David Gibson
` (22 preceding siblings ...)
2021-01-06 6:12 ` [PULL 00/22] ppc-for-6.0 queue 20210106 BALATON Zoltan via
@ 2021-01-06 13:30 ` Peter Maydell
2021-01-06 15:29 ` BALATON Zoltan via
23 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2021-01-06 13:30 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, Greg Kurz, QEMU Developers
On Wed, 6 Jan 2021 at 03:38, David Gibson <david@gibson.dropbear.id.au> wrote:
>
> The following changes since commit 52d25464605dc20022ad94aa8bc8e8473e600833:
>
> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210104' into staging (2021-01-05 16:18:20 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/dgibson/qemu.git tags/ppc-for-6.0-20210106
>
> for you to fetch changes up to 5cbd51a5a58098444ffa246ece2013849be04299:
>
> ppc440_pcix: Fix up pci config access (2021-01-06 11:09:59 +1100)
>
> ----------------------------------------------------------------
> ppc patch queue 2021-01-06
>
> First pull request for 2021, which has a bunch of things accumulated
> over the holidays. Includes:
> * A number of cleanups to sam460ex and ppc440 code from BALATON Zoltan
> * Several fixes for builds with --without-default-devices from Greg Kurz
> * Fixes for some DRC reset problems from Greg Kurz
> * QOM conversion of the PPC 4xx UIC devices from Peter Maydell
> * Some other assorted fixes and cleanups
>
> ----------------------------------------------------------------
> BALATON Zoltan via (5):
> ppc4xx: Move common dependency on serial to common option
> sam460ex: Remove FDT_PPC dependency from KConfig
> ppc440_pcix: Improve comment for IRQ mapping
> ppc440_pcix: Fix register write trace event
> ppc440_pcix: Fix up pci config access
Applied, thanks. I'm afraid I missed reading Balaton's email
before pushing this to master, so the whole set is in there;
sorry about that. Would you mind sending a patchset that
makes the necessary changes on top of master (reverts or fixes
as appropriate)?
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PULL 00/22] ppc-for-6.0 queue 20210106
2021-01-06 13:30 ` Peter Maydell
@ 2021-01-06 15:29 ` BALATON Zoltan via
0 siblings, 0 replies; 26+ messages in thread
From: BALATON Zoltan via @ 2021-01-06 15:29 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, qemu-ppc, Greg Kurz, David Gibson
On Wed, 6 Jan 2021, Peter Maydell wrote:
> On Wed, 6 Jan 2021 at 03:38, David Gibson <david@gibson.dropbear.id.au> wrote:
>>
>> The following changes since commit 52d25464605dc20022ad94aa8bc8e8473e600833:
>>
>> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210104' into staging (2021-01-05 16:18:20 +0000)
>>
>> are available in the Git repository at:
>>
>> https://gitlab.com/dgibson/qemu.git tags/ppc-for-6.0-20210106
>>
>> for you to fetch changes up to 5cbd51a5a58098444ffa246ece2013849be04299:
>>
>> ppc440_pcix: Fix up pci config access (2021-01-06 11:09:59 +1100)
>>
>> ----------------------------------------------------------------
>> ppc patch queue 2021-01-06
>>
>> First pull request for 2021, which has a bunch of things accumulated
>> over the holidays. Includes:
>> * A number of cleanups to sam460ex and ppc440 code from BALATON Zoltan
>> * Several fixes for builds with --without-default-devices from Greg Kurz
>> * Fixes for some DRC reset problems from Greg Kurz
>> * QOM conversion of the PPC 4xx UIC devices from Peter Maydell
>> * Some other assorted fixes and cleanups
>>
>> ----------------------------------------------------------------
>> BALATON Zoltan via (5):
>> ppc4xx: Move common dependency on serial to common option
>> sam460ex: Remove FDT_PPC dependency from KConfig
>> ppc440_pcix: Improve comment for IRQ mapping
>> ppc440_pcix: Fix register write trace event
>> ppc440_pcix: Fix up pci config access
>
>
> Applied, thanks. I'm afraid I missed reading Balaton's email
> before pushing this to master, so the whole set is in there;
> sorry about that. Would you mind sending a patchset that
> makes the necessary changes on top of master (reverts or fixes
> as appropriate)?
Sent a fixup series with the two reverts and the missing patch.
Regards,
BALATON Zoltan
> Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
> for any user-visible changes.
>
> -- PMM
>
>
^ permalink raw reply [flat|nested] 26+ messages in thread