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From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 17/20] target/arm: Implement SG instruction
Date: Thu, 5 Oct 2017 14:50:17 -0400	[thread overview]
Message-ID: <cd16f792-28a0-95b8-6a68-73f1427e6d38@linaro.org> (raw)
In-Reply-To: <1506092407-26985-18-git-send-email-peter.maydell@linaro.org>

On 09/22/2017 11:00 AM, Peter Maydell wrote:
> Implement the SG instruction, which we emulate 'by hand' in the
> exception handling code path.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target/arm/helper.c | 129 ++++++++++++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 124 insertions(+), 5 deletions(-)
> 
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index b1ecb66..8df819d 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -41,6 +41,10 @@ typedef struct V8M_SAttributes {
>      bool irvalid;
>  } V8M_SAttributes;
>  
> +static void v8m_security_lookup(CPUARMState *env, uint32_t address,
> +                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
> +                                V8M_SAttributes *sattrs);
> +
>  /* Definitions for the PMCCNTR and PMCR registers */
>  #define PMCRD   0x8
>  #define PMCRC   0x4
> @@ -6724,6 +6728,123 @@ static void arm_log_exception(int idx)
>      }
>  }
>  
> +static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, uint16_t *insn)
> +{

This function doesn't take an address ...

> +    if (get_phys_addr(env, env->regs[15], MMU_INST_FETCH, mmu_idx,
> +                      &physaddr, &attrs, &prot, &page_size, &fsr, &fi)) {

... reading it directly from r15 ...

> +    if (insn != 0xe97f) {
> +        /* Not an SG instruction first half (we choose the IMPDEF
> +         * early-SG-check option).
> +         */
> +        goto gen_invep;
> +    }
> +
> +    if (!v7m_read_half_insn(cpu, mmu_idx, &insn)) {
> +        return false;
> +    }
> +
> +    if (insn != 0xe97f) {
> +        /* Not an SG instruction second half */
> +        goto gen_invep;
> +    }

... but somehow expects to get two different values read from the same address?

Certainly you'd get the wrong exception frame if you incremented r15 in between.

> +    env->regs[15] += 4;

... that make this right and the implicit address to the readers wrong.

I don't see anything else amiss in the patch.


r~

  parent reply	other threads:[~2017-10-05 18:50 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-22 14:59 [Qemu-devel] [PATCH 00/20] ARM v8M: exception entry, exit and security Peter Maydell
2017-09-22 14:59 ` [Qemu-devel] [PATCH 01/20] nvic: Clear the vector arrays and prigroup on reset Peter Maydell
2017-09-23  0:34   ` Richard Henderson
2017-09-29 21:03   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-09-22 14:59 ` [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target stack early in v7M exception return Peter Maydell
2017-10-05  4:44   ` Philippe Mathieu-Daudé
2017-10-05 16:04   ` Richard Henderson
2017-10-05 16:20     ` Peter Maydell
2017-10-06 13:22       ` Peter Maydell
2017-10-06 13:24         ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 03/20] target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode Peter Maydell
2017-10-05  3:25   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 16:09   ` [Qemu-devel] " Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 04/20] target/arm: Restore security state on exception return Peter Maydell
2017-10-05 16:14   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 05/20] target/arm: Restore SPSEL to correct CONTROL register " Peter Maydell
2017-10-05 16:18   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 06/20] target/arm: Check for xPSR mismatch usage faults earlier for v8M Peter Maydell
2017-10-05 16:25   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 07/20] target/arm: Warn about restoring to unaligned stack Peter Maydell
2017-09-29 21:05   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 16:28   ` [Qemu-devel] " Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 08/20] target/arm: Don't warn about exception return with PC low bit set for v8M Peter Maydell
2017-09-29 21:07   ` Philippe Mathieu-Daudé
2017-10-05 16:32   ` Richard Henderson
2017-10-05 16:34     ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 09/20] target/arm: Add new-in-v8M SFSR and SFAR Peter Maydell
2017-10-05 16:39   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 10/20] target/arm: Update excret sanity checks for v8M Peter Maydell
2017-10-05 17:16   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 11/20] target/arm: Add support for restoring v8M additional state context Peter Maydell
2017-10-05 17:30   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 12/20] target/arm: Add v8M support to exception entry code Peter Maydell
2017-10-05 18:31   ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 13/20] nvic: Implement Security Attribution Unit registers Peter Maydell
2017-10-05 18:33   ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 14/20] target/arm: Implement security attribute lookups for memory accesses Peter Maydell
2017-10-05 18:39   ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 15/20] target/arm: Fix calculation of secure mm_idx values Peter Maydell
2017-10-05  4:46   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 18:41   ` [Qemu-devel] " Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 16/20] target/arm: Factor out "get mmuidx for specified security state" Peter Maydell
2017-10-05  3:29   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 18:42   ` [Qemu-devel] " Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 17/20] target/arm: Implement SG instruction Peter Maydell
2017-09-22 17:18   ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2017-10-05 18:50   ` Richard Henderson [this message]
2017-10-05 18:55     ` [Qemu-devel] " Peter Maydell
2017-10-05 18:57       ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 18/20] target/arm: Implement BLXNS Peter Maydell
2017-10-05 13:07   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 18:56   ` [Qemu-devel] " Richard Henderson
2017-10-05 19:40     ` Peter Maydell
2017-09-22 15:00 ` [Qemu-devel] [PATCH 19/20] target/arm: Implement secure function return Peter Maydell
2017-10-05 13:11   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 19:00   ` [Qemu-devel] " Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 20/20] nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit Peter Maydell
2017-10-05  4:33   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 19:01   ` [Qemu-devel] " Richard Henderson
2017-10-05  4:51 ` [Qemu-devel] [Qemu-arm] [PATCH 00/20] ARM v8M: exception entry, exit and security Philippe Mathieu-Daudé
2017-10-06 13:29 ` Peter Maydell

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