Re: [PATCH 4/4] hw/arm/aspeed: Add GB200 BMC target

["Cédric Le Goater" <clg@kaod.org>]

On 7/1/25 22:34, Ed Tanous wrote:
> GB200nvl72 is a system for for accelerated compute.  This is a model for
> the BMC target within the system.

Could you please add a comment saying it is based on DT :

   aspeed-bmc-nvidia-gb200nvl-bmc.dts

from

   https://github.com/openbmc/linux/blob/dev-6.6/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts


> Signed-off-by: Ed Tanous <etanous@nvidia.com>
> ---
>   hw/arm/aspeed.c        | 79 ++++++++++++++++++++++++++++++++++++++++++
>   hw/arm/aspeed_eeprom.c | 21 +++++++++++
>   hw/arm/aspeed_eeprom.h |  3 ++
>   3 files changed, 103 insertions(+)
> 
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 3ef7f6c5b2..98144ced86 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -19,6 +19,7 @@
>   #include "hw/i2c/i2c_mux_pca954x.h"
>   #include "hw/i2c/smbus_eeprom.h"
>   #include "hw/gpio/pca9552.h"
> +#include "hw/gpio/pca9554.h"
>   #include "hw/nvram/eeprom_at24c.h"
>   #include "hw/sensor/tmp105.h"
>   #include "hw/misc/led.h"
> @@ -201,6 +202,10 @@ struct AspeedMachineState {
>   #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
>   #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
>   
> +/* GB200NVL hardware value */
> +#define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
> +#define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
> +
>   /* Qualcomm DC-SCM hardware value */
>   #define QCOM_DC_SCM_V1_BMC_HW_STRAP1  0x00000000
>   #define QCOM_DC_SCM_V1_BMC_HW_STRAP2  0x00000041
> @@ -647,6 +652,12 @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
>                               TYPE_PCA9552, addr);
>   }
>   
> +static I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr)
> +{
> +    return i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
> +                            TYPE_PCA9554, addr);
> +}
> +
>   static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
>   {
>       AspeedSoCState *soc = bmc->soc;
> @@ -1052,6 +1063,45 @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
>       i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
>   }
>   
> +> +static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
> +{
> +    AspeedSoCState *soc = bmc->soc;
> +    I2CBus *i2c[15] = {};
> +    DeviceState *dev;
> +    for (int i = 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) {
> +        if ((i == 11) || (i == 12) || (i == 13)) {
> +            continue;
> +        }
> +        i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
> +    }
> +
> +    /* Bus 5 Expander */
> +    create_pca9554(soc, 4, 0x21);
> +
> +    /* Mux I2c Expanders */
> +    i2c_slave_create_simple(i2c[5], "pca9546", 0x71);
> +    i2c_slave_create_simple(i2c[5], "pca9546", 0x72);
> +    i2c_slave_create_simple(i2c[5], "pca9546", 0x73);
> +    i2c_slave_create_simple(i2c[5], "pca9546", 0x75);
> +    i2c_slave_create_simple(i2c[5], "pca9546", 0x76);
> +    i2c_slave_create_simple(i2c[5], "pca9546", 0x77);
> +
> +    /* Bus 10 */
> +    dev = DEVICE(create_pca9554(soc, 9, 0x20));
> +
> +    /* Set FPGA_READY */
> +    object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal);
> +
> +    create_pca9554(soc, 9, 0x21);
> +    at24c_eeprom_init(i2c[9], 0x50, 64 * KiB);
> +    at24c_eeprom_init(i2c[9], 0x51, 64 * KiB);
> +
> +    /* Bus 11 */
> +    at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid,
> +                          gb200nvl_bmc_fruid_len);
> +}
> +
>   static void fby35_i2c_init(AspeedMachineState *bmc)
>   {
>       AspeedSoCState *soc = bmc->soc;
> @@ -1587,6 +1637,31 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc,
>       aspeed_machine_class_init_cpus_defaults(mc);
>   }
>   
> +#define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB)
> +
> +static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc,
> +                                               const void *data)
> +{
> +    MachineClass *mc = MACHINE_CLASS(oc);
> +    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
> +
> +    mc->desc       = "Nvidia GB200NVL BMC (Cortex-A7)";
> +    amc->soc_name  = "ast2600-a3";
> +    amc->hw_strap1 = GB200NVL_BMC_HW_STRAP1;
> +    amc->hw_strap2 = GB200NVL_BMC_HW_STRAP2;
> +    amc->fmc_model = "mx66u51235f";
> +    amc->spi_model = "mx66u51235f";
> +    amc->num_cs    = 2;
> +
> +    amc->spi2_model = "mx66u51235f";
> +    amc->num_cs2   = 1;
> +    amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> +    amc->i2c_init  = gb200nvl_bmc_i2c_init;
> +    mc->default_ram_size = GB200NVL_BMC_RAM_SIZE;
> +    aspeed_machine_class_init_cpus_defaults(mc);
> +    aspeed_machine_ast2600_class_emmc_init(oc);
> +}
> +
>   static void fby35_reset(MachineState *state, ResetType type)
>   {
>       AspeedMachineState *bmc = ASPEED_MACHINE(state);
> @@ -1879,6 +1954,10 @@ static const TypeInfo aspeed_machine_types[] = {
>           .name          = MACHINE_TYPE_NAME("bletchley-bmc"),
>           .parent        = TYPE_ASPEED_MACHINE,
>           .class_init    = aspeed_machine_bletchley_class_init,
> +    }, {
> +        .name          = MACHINE_TYPE_NAME("gb200nvl-bmc"),
> +        .parent        = TYPE_ASPEED_MACHINE,
> +        .class_init    = aspeed_machine_gb200nvl_class_init,
>       }, {
>           .name          = MACHINE_TYPE_NAME("fby35-bmc"),
>           .parent        = MACHINE_TYPE_NAME("ast2600-evb"),
> diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c
> index daa3d329d1..8bbbdec834 100644
> --- a/hw/arm/aspeed_eeprom.c
> +++ b/hw/arm/aspeed_eeprom.c
> @@ -162,6 +162,25 @@ const uint8_t rainier_bmc_fruid[] = {
>       0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
>   };
>   
> +const uint8_t gb200nvl_bmc_fruid[] = {
> +    0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x1f,
> +    0x0f, 0xe6, 0xc6, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0xc5, 0x50, 0x33,
> +    0x38, 0x30, 0x39, 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38,
> +    0x30, 0x30, 0x31, 0x35, 0x30, 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33,
> +    0x38, 0x30, 0x39, 0x2d, 0x30, 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30,
> +    0xc0, 0x01, 0x01, 0xd6, 0x4d, 0x41, 0x43, 0x3a, 0x20, 0x33, 0x43, 0x3a,
> +    0x36, 0x44, 0x3a, 0x36, 0x36, 0x3a, 0x31, 0x34, 0x3a, 0x43, 0x38, 0x3a,
> +    0x37, 0x41, 0xc1, 0x3b, 0x01, 0x09, 0x19, 0xc6, 0x4e, 0x56, 0x49, 0x44,
> +    0x49, 0x41, 0xc9, 0x50, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x42, 0x4d, 0x43,
> +    0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x30,
> +    0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, 0xc4, 0x41, 0x45, 0x2e, 0x31,
> +    0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, 0x30, 0x30, 0x31,
> +    0x35, 0x30, 0xc0, 0xc4, 0x76, 0x30, 0x2e, 0x31, 0xc1, 0x00, 0x00, 0x00,
> +    0x00, 0x00, 0x00, 0xb4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
> +
> +};
> +
>   const size_t tiogapass_bmc_fruid_len = sizeof(tiogapass_bmc_fruid);
>   const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid);
>   const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid);
> @@ -169,3 +188,5 @@ const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid);
>   const size_t yosemitev2_bmc_fruid_len = sizeof(yosemitev2_bmc_fruid);
>   const size_t rainier_bb_fruid_len = sizeof(rainier_bb_fruid);
>   const size_t rainier_bmc_fruid_len = sizeof(rainier_bmc_fruid);
> +const size_t gb200nvl_bmc_fruid_len = sizeof(gb200nvl_bmc_fruid);
> +
> diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h
> index f08c16ef50..3ed9bc1d9a 100644
> --- a/hw/arm/aspeed_eeprom.h
> +++ b/hw/arm/aspeed_eeprom.h
> @@ -26,4 +26,7 @@ extern const size_t rainier_bb_fruid_len;
>   extern const uint8_t rainier_bmc_fruid[];
>   extern const size_t rainier_bmc_fruid_len;
>   
> +extern const uint8_t gb200nvl_bmc_fruid[];
> +extern const size_t gb200nvl_bmc_fruid_len;
> +
>   #endif