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[37.14.164.149]) by smtp.gmail.com with ESMTPSA id k37sm16236627wms.21.2021.11.29.02.47.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Nov 2021 02:47:20 -0800 (PST) Subject: Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target To: =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20211128135719.50444-1-frederic.petrot@univ-grenoble-alpes.fr> From: Richard Henderson Message-ID: Date: Mon, 29 Nov 2021 11:47:17 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20211128135719.50444-1-frederic.petrot@univ-grenoble-alpes.fr> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32d (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.317, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: philmd@redhat.com, bin.meng@windriver.com, alistair.francis@wdc.com, palmer@dabbelt.com, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/28/21 2:57 PM, Frédéric Pétrot wrote: > This series of patches provides partial 128-bit support for the riscv > target architecture, namely RVI and RVM, with minimal csr support. > > Thanks again for the reviews and suggestions. > > v6: > - support for '-cpu rv128' in qemu-system-riscv64 to handle 128-bit > executables (no more qemu-system-riscv128) > - remove useless (and buggy) big-endian support in lq/sq It seems like you haven't tested this with linux-user? There are build problems: In file included from /home/rth/qemu/qemu/include/semihosting/console.h:12, from ../qemu/linux-user/semihost.c:14: ../qemu/target/riscv/cpu.h:485:33: error: unknown type name ‘Int128’ 485 | Int128 *ret_value, | ^~~~~~ ../qemu/target/riscv/cpu.h:486:33: error: unknown type name ‘Int128’ 486 | Int128 new_value, Int128 write_mask); | ^~~~~~ ../qemu/target/riscv/cpu.h:486:51: error: unknown type name ‘Int128’ 486 | Int128 new_value, Int128 write_mask); | ^~~~~~ ../qemu/target/riscv/cpu.h:489:48: error: unknown type name ‘Int128’ 489 | Int128 *ret_value); | ^~~~~~ ../qemu/target/riscv/cpu.h:491:46: error: unknown type name ‘Int128’ 491 | Int128 new_value); | ^~~~~~ ../qemu/target/riscv/cpu.h:499:5: error: unknown type name ‘riscv_csr_read128_fn’ 499 | riscv_csr_read128_fn read128; | ^~~~~~~~~~~~~~~~~~~~ ../qemu/target/riscv/cpu.h:500:5: error: unknown type name ‘riscv_csr_write128_fn’ 500 | riscv_csr_write128_fn write128; | ^~~~~~~~~~~~~~~~~~~~~ ninja: build stopped: subcommand failed. r~