Re: [PATCH 05/21] hw/dma/zynq: Notify devcfg on FPGA reset via SLCR control

["Corvin Köhne" <C.Koehne@beckhoff.com>]

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On Fri, 2025-04-25 at 18:11 +0200, Edgar E. Iglesias wrote:
> CAUTION: External Email!!
> On Tue, Mar 18, 2025 at 02:07:56PM +0100, Corvin Köhne wrote:
> > From: YannickV <Y.Vossen@beckhoff.com>
> > 
> > When the FPGA_RST_CTRL register in the SLCR (System Level Control
> > Register) is written to, the devcfg (Device Configuration) should
> > indicate the finished reset.
> > 
> > Problems occure when Loaders trigger a reset via SLCR and poll for
> > the done flag in devcfg. Since the flag will never be set, this can
> > result in an endless loop.
> > 
> > A callback function `slcr_reset_handler` is added to the
> > `XlnxZynqDevcfg` structure. The `slcr_reset` function sets the
> > `PCFG_DONE` flag when triggered by an FPGA reset in the SLCR.
> > The SLCR write handler calls the `slcr_reset` function when the
> > FPGA reset control register (`R_FPGA_RST_CTRL`) is written with
> > the reset value.
> 
> Could you please refer to the specs where this is described?
> I couldn't find it...
> 
> 

Looks like we've misread the specs and our loader code. Our loader writes a one
to PCFG_DONE and FPGA_RST_CTRL and then polls PCFG_DONE, so we thought that it's
related. However, we've rechecked it and on hardware PCFG_DONE isn't reset on
this write. According to the spec, PCFG_DONE is a Write 1 to Clear register but
it won't reset when the condition for setting PCFG_DONE is still true. We're
going to fix this in v2, thanks.


-- 
Kind regards,
Corvin

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