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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id s130sm4368967pgc.82.2019.12.11.18.09.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Dec 2019 18:09:15 -0800 (PST) Subject: Re: [PATCH v3 11/20] target/arm: default SVE length to 64 bytes for linux-user To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-12-alex.bennee@linaro.org> From: Richard Henderson Message-ID: Date: Wed, 11 Dec 2019 18:09:13 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191211170520.7747-12-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" , luis.machado@linaro.org, alan.hayward@arm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/11/19 9:05 AM, Alex Bennée wrote: > The Linux kernel chooses the default of 64 bytes for SVE registers on > the basis that it is the largest size on known hardware that won't > grow the signal frame. We still honour the sve-max-vq property and > userspace can expand the number of lanes by calling PR_SVE_SET_VL. > > This should not make any difference to SVE enabled software as the SVE > is of course vector length agnostic. > > Signed-off-by: Alex Bennée > > --- > v2 > - tweak zcr_el[1] instead > --- > target/arm/cpu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 7a4ac9339bf..d42b88c9b73 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -199,9 +199,9 @@ static void arm_cpu_reset(CPUState *s) > /* and to the SVE instructions */ > env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); > env->cp15.cptr_el[3] |= CPTR_EZ; > - /* with maximum vector length */ > + /* with reasonable vector length */ I think this comment should mention the kernel as well. Otherwise, Reviewed-by: Richard Henderson r~