From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v1 3/3] target/riscv: Regen floating point rounding mode in dynamic mode
Date: Tue, 30 Jun 2020 14:51:36 -0700 [thread overview]
Message-ID: <cd66f31b-2c07-da29-c14c-5f1079e016e3@linaro.org> (raw)
In-Reply-To: <ea4f280e6f77e734c8e555e3c98d10085ce9f5b6.1593547870.git.alistair.francis@wdc.com>
On 6/30/20 1:12 PM, Alistair Francis wrote:
> When a guest specificies the the rounding mode should be dynamic 0b111
> then we want to re-caclulate the rounding mode on each instruction. The
> gen_helper_set_rounding_mode() function will correctly check the
> rounding mode and handle a dynamic rounding, we just need to make sure
> it's always called if dynamic rounding is selected.
>
> Fixes: 1885350 ("RISCV dynamic rounding mode is not behaving correctly")
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index ce71ca7a92..a39eba679a 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -490,7 +490,7 @@ static void gen_set_rm(DisasContext *ctx, int rm)
> {
> TCGv_i32 t0;
>
> - if (ctx->frm == rm) {
> + if (ctx->frm == rm && rm != 7) {
> return;
This should not be necessary.
It was my understanding that after the set to the csr, that we would end the
TB. That's certainly what I see in RISCV_OP_CSR_POST.
The next TB will begin wiht ctx->frm = -1, so we will reset the rounding mode
with 7. It would be good to understand what's really going on here.
r~
next prev parent reply other threads:[~2020-06-30 21:52 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-30 20:12 [PATCH v1 0/3] A few RISC-V fixes Alistair Francis
2020-06-30 20:12 ` [PATCH v1 1/3] hw/char: Convert the Ibex UART to use the qdev Clock model Alistair Francis
2020-07-03 7:42 ` Philippe Mathieu-Daudé
2020-07-07 17:20 ` Alistair Francis
2020-06-30 20:12 ` [PATCH v1 2/3] hw/riscv: Allow 64 bit access to SiFive CLINT Alistair Francis
2020-07-01 0:19 ` LIU Zhiwei
2020-07-02 3:33 ` Alistair Francis
2020-07-03 7:44 ` Philippe Mathieu-Daudé
2020-06-30 20:12 ` [PATCH v1 3/3] target/riscv: Regen floating point rounding mode in dynamic mode Alistair Francis
2020-06-30 21:51 ` Richard Henderson [this message]
2020-07-01 0:17 ` LIU Zhiwei
2020-07-03 1:24 ` Bin Meng
2020-07-07 17:23 ` Alistair Francis
2020-07-08 0:36 ` Bin Meng
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