From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.33) id 1CCPAI-00013i-Tt for qemu-devel@nongnu.org; Tue, 28 Sep 2004 17:05:38 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.33) id 1CCPAI-00013O-9M for qemu-devel@nongnu.org; Tue, 28 Sep 2004 17:05:38 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.33) id 1CCPAI-00013E-7A for qemu-devel@nongnu.org; Tue, 28 Sep 2004 17:05:38 -0400 Received: from [64.233.170.194] (helo=mproxy.gmail.com) by monty-python.gnu.org with esmtp (Exim 4.34) id 1CCP3i-0004Rr-KM for qemu-devel@nongnu.org; Tue, 28 Sep 2004 16:58:50 -0400 Received: by mproxy.gmail.com with SMTP id 73so37177rnl for ; Tue, 28 Sep 2004 13:58:13 -0700 (PDT) Message-ID: Date: Tue, 28 Sep 2004 16:58:12 -0400 From: Karl Magdsick Subject: Re: [Qemu-devel] ix64 target support In-Reply-To: <1096390325.4234.365.camel@fred.soliddesign.net> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit References: <1096390325.4234.365.camel@fred.soliddesign.net> Reply-To: Karl Magdsick , qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org There is the ia64 architecture (Itanium) and the amd64 architecture (Opteron, Athlon64, formerly known as x86_64). (The Linux kernel still uses the old architecture name, but some linux (??most??) distributions have adopted the manufacturer's official name for the architecture.) I assume you're talking about amd64. QEMU is capable of emulating PPC on x86, so the extra number of registers on amd64 as opposed to x86 is not an issue. Each 64 bit register would, of course have to be treated as a pair of 32-bit registers on 32-bit platforms, of course. I have read that QEMU does not emulate the MMU (at least with some target/host combinations), but you will probably need to emulate a 64-bit MMU on 32-bit platforms. (Actually, I've read that current amd64 chips actually use 40-bit addressing internally, so you only need to emulate a 40-bit MMU. I would personally not intentionally emulate the limitations of the current batch of chips if the processor family clearly is intended to go beyond these limitations in the future.) While we're on the subject of future plans for QEMU, I've read that QEMU makes no attempts at optimal register allocation. Are there plans to change this in the future? I've heard the arguments about debugging, but I've heard that debuggers are refusing to debug the translated code anyway. Cheers, -Karl On Tue, 28 Sep 2004 11:52:05 -0500, Joe Batt wrote: > I have a project that I'd like to code for 64 bit memory addressing (big > pointers). I will eventually purchase 64 bit equipment, but I'd like to > do a feasibility test first. > > qemu doesn't yet support a ix64 target. How far are we from that? Is > anyone working on it? Is it as simple as implementing some extra > opcodes or are there fundamental issues? > > I've implemented a simple sh2 emulator in a previous project; I > understand just a little of how qemu might work. I may be able to help. > > Thanks, > Joe > > _______________________________________________ > Qemu-devel mailing list > Qemu-devel@nongnu.org > http://lists.nongnu.org/mailman/listinfo/qemu-devel >