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([2001:8003:c020:6900:12c1:9684:874a:fb3a]) by smtp.gmail.com with ESMTPSA id c13-20020aa781cd000000b006d9fd64fdcasm1975921pfn.37.2023.12.27.15.06.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Dec 2023 15:06:32 -0800 (PST) Message-ID: Date: Thu, 28 Dec 2023 10:06:27 +1100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 24/35] target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2 Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20231218113305.2511480-1-peter.maydell@linaro.org> <20231218113305.2511480-25-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20231218113305.2511480-25-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/18/23 22:32, Peter Maydell wrote: > With FEAT_NV2, the condition for when SPSR_EL1.M should report that > an exception was taken from EL2 changes. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 45444360f95..38e16c2f8a5 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -11405,10 +11405,18 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) > aarch64_save_sp(env, arm_current_el(env)); > env->elr_el[new_el] = env->pc; > > - if (cur_el == 1 && new_el == 1 && > - ((arm_hcr_el2_eff(env) & (HCR_NV | HCR_NV1)) == HCR_NV)) { > - /* I_ZJRNN: report EL2 in the SPSR by setting M[3:2] to 0b10 */ > - old_mode = deposit32(old_mode, 2, 2, 2); > + if (cur_el == 1 && new_el == 1) { > + uint64_t hcr = arm_hcr_el2_eff(env); > + if ((hcr & (HCR_NV | HCR_NV1 | HCR_NV2)) == HCR_NV || > + (hcr & (HCR_NV | HCR_NV2)) == (HCR_NV | HCR_NV2)) { Maybe clearer as if ((hcr & HCR_NV) && ((hcr & HCR_NV2) || !(hcr & HCR_NV1))) ? Anyway, Reviewed-by: Richard Henderson r~ > + /* > + * FEAT_NV, FEAT_NV2 may need to report EL2 in the SPSR > + * by setting M[3:2] to 0b10. > + * If NV2 is disabled, change SPSR when NV,NV1 == 1,0 (I_ZJRNN) > + * If NV2 is enabled, change SPSR when NV is 1 (I_DBTLM) > + */ > + old_mode = deposit32(old_mode, 2, 2, 2); > + } > } > } else { > old_mode = cpsr_read_for_spsr_elx(env);