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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2aba822b615sm35906621eec.0.2025.12.08.09.18.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Dec 2025 09:18:07 -0800 (PST) Message-ID: Date: Mon, 8 Dec 2025 18:17:55 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 29/33] hw/arm/smmuv3-accel: Add property to specify OAS bits Content-Language: en-US To: Nicolin Chen , Shameer Kolothum Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, peter.maydell@linaro.org, jgg@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, yi.l.liu@intel.com, kjaju@nvidia.com References: <20251120132213.56581-1-skolothumtho@nvidia.com> <20251120132213.56581-30-skolothumtho@nvidia.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/20/25 10:47 PM, Nicolin Chen wrote: > On Thu, Nov 20, 2025 at 01:22:09PM +0000, Shameer Kolothum wrote: >> QEMU SMMUv3 currently sets the output address size (OAS) to 44 bits. >> With accelerator mode enabled, a device may use SVA, where CPU page tables >> are shared with the SMMU, requiring an OAS at least as large as the >> CPU’s output address size. A user option is added to configure this. >> >> However, the OAS value advertised by the virtual SMMU must remain >> compatible with the capabilities of the host SMMUv3. In accelerated >> mode, the host SMMU performs stage-2 translation and must be able to >> consume the intermediate physical addresses (IPA) produced by stage-1. >> >> The OAS exposed by the virtual SMMU defines the maximum IPA width that >> stage-1 translations may generate. For AArch64 implementations, the >> maximum usable IPA size on the host SMMU is determined by its own OAS. >> Check that the configured OAS does not exceed what the host SMMU >> can safely support. >> >> Tested-by: Zhangfei Gao >> Signed-off-by: Shameer Kolothum >> --- >> hw/arm/smmuv3-accel.c | 20 ++++++++++++++++++++ >> hw/arm/smmuv3-internal.h | 3 ++- >> hw/arm/smmuv3.c | 16 +++++++++++++++- >> include/hw/arm/smmuv3.h | 1 + >> 4 files changed, 38 insertions(+), 2 deletions(-) >> >> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c >> index 73c7ce586a..35a94c720a 100644 >> --- a/hw/arm/smmuv3-accel.c >> +++ b/hw/arm/smmuv3-accel.c >> @@ -27,6 +27,12 @@ >> static MemoryRegion root, sysmem; >> static AddressSpace *shared_as_sysmem; >> >> +static int smmuv3_oas_bits(uint32_t oas) >> +{ >> + static const int map[] = { 32, 36, 40, 42, 44, 48, 52, 56 }; >> + return () ? map[oas] : -EINVAL; > We should probably just: > g_assert(oas < ARRAY_SIZE(map)); > > -EINVAL is useless anyway in the caller that prints it. > > Otherwise, > > Reviewed-by: Nicolin Chen With Nicolin's suggestion Reviewed-by: Eric Auger Eric >