From: "Cédric Le Goater" <clg@redhat.com>
To: Glenn Miles <milesg@linux.ibm.com>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com,
thuth@redhat.com, rathc@linux.ibm.com,
richard.henderson@linaro.org
Subject: Re: [PATCH v3 8/9] hw/ppc: Add a test machine for the IBM PPE42 CPU
Date: Wed, 10 Sep 2025 09:10:30 +0200 [thread overview]
Message-ID: <ce46413b-dab9-4ffc-9e6e-078c6b2ed6b9@redhat.com> (raw)
In-Reply-To: <20250908200028.115789-9-milesg@linux.ibm.com>
On 9/8/25 22:00, Glenn Miles wrote:
> Adds a test machine for the IBM PPE42 processor, including a
> DEC, FIT, WDT and 512 KiB of ram.
>
> The purpose of this machine is only to provide a generic platform
> for testing instructions of the recently added PPE42 processor
> model which is used extensively in the IBM Power9, Power10 and
> future Power server processors.
>
> Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
> ---
>
> Changes from v2:
> - Moved decrementer changes to distinct commit
> - Introduced a specific MachineState for the ppe42 Machine
> - Use qdev_realize to create the machine
> - Use valid_cpu_types to determine validity of CPU
> - Changed machine ram limit from 2GB to 512KB
>
> MAINTAINERS | 6 +++
> hw/ppc/Kconfig | 9 ++++
> hw/ppc/meson.build | 2 +
> hw/ppc/ppe42_machine.c | 102 +++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 119 insertions(+)
> create mode 100644 hw/ppc/ppe42_machine.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a07086ed76..52fa303e0a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1531,6 +1531,12 @@ F: include/hw/pci-host/grackle.h
> F: pc-bios/qemu_vga.ndrv
> F: tests/functional/test_ppc_mac.py
>
> +PPE42
> +M: Glenn Miles <milesg@linux.ibm.com>
> +L: qemu-ppc@nongnu.org
> +S: Odd Fixes
> +F: hw/ppc/ppe42_machine.c
> +
> PReP
> M: Hervé Poussineau <hpoussin@reactos.org>
> L: qemu-ppc@nongnu.org
> diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
> index ced6bbc740..3fdea5919c 100644
> --- a/hw/ppc/Kconfig
> +++ b/hw/ppc/Kconfig
> @@ -44,6 +44,15 @@ config POWERNV
> select SSI_M25P80
> select PNV_SPI
>
> +config PPC405
> + bool
> + default y
> + depends on PPC
> + select M48T59
> + select PFLASH_CFI02
> + select PPC4XX
> + select SERIAL
Does the machine need all the above support ?
> +
> config PPC440
> bool
> default y
> diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
> index 9893f8adeb..170b90ae7d 100644
> --- a/hw/ppc/meson.build
> +++ b/hw/ppc/meson.build
> @@ -57,6 +57,8 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
> 'pnv_n1_chiplet.c',
> ))
> # PowerPC 4xx boards
> +ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
> + 'ppe42_machine.c'))
> ppc_ss.add(when: 'CONFIG_PPC440', if_true: files(
> 'ppc440_bamboo.c',
> 'ppc440_uc.c'))
> diff --git a/hw/ppc/ppe42_machine.c b/hw/ppc/ppe42_machine.c
> new file mode 100644
> index 0000000000..2cfce2503f
> --- /dev/null
> +++ b/hw/ppc/ppe42_machine.c
> @@ -0,0 +1,102 @@
> +/*
> + * Test Machine for the IBM PPE42 processor
> + *
> + * Copyright (c) 2025, IBM Corporation.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/units.h"
> +#include "qemu/error-report.h"
> +#include "system/address-spaces.h"
> +#include "hw/boards.h"
> +#include "hw/ppc/ppc.h"
> +#include "system/system.h"
> +#include "system/reset.h"
> +#include "system/kvm.h"
> +#include "qapi/error.h"
> +
> +#define TYPE_PPE42_MACHINE MACHINE_TYPE_NAME("ppe42_machine")
> +typedef MachineClass Ppe42MachineClass;
> +typedef struct Ppe42MachineState Ppe42MachineState;
> +DECLARE_OBJ_CHECKERS(Ppe42MachineState, Ppe42MachineClass,
> + PPE42_MACHINE, TYPE_PPE42_MACHINE)
> +
> +struct Ppe42MachineState {
> + MachineState parent_obj;
> +
> + PowerPCCPU cpu;
> +};
> +
> +static void main_cpu_reset(void *opaque)
> +{
> + PowerPCCPU *cpu = opaque;
> +
> + cpu_reset(CPU(cpu));
> +}
> +
> +static void ppe42_machine_init(MachineState *machine)
> +{
> + Ppe42MachineState *pms = PPE42_MACHINE(machine);
> + PowerPCCPU *cpu = &pms->cpu;
> +
> + if (kvm_enabled()) {
> + error_report("machine %s does not support the KVM accelerator",
> + MACHINE_GET_CLASS(machine)->name);
> + exit(EXIT_FAILURE);
> + }
> +
> + /* init CPU */
> + object_initialize_child(OBJECT(pms), "cpu", cpu, machine->cpu_type);
> + if (!qdev_realize(DEVICE(cpu), NULL, &error_fatal)) {
> + return;
> + }
> +
> + qemu_register_reset(main_cpu_reset, cpu);
> +
> + /* This sets the decrementer timebase */
> + ppc_booke_timers_init(cpu, 37500000, PPC_TIMER_PPE);
> +
> + /* RAM */
> + if (machine->ram_size > 512 * KiB) {
> + error_report("RAM size more than 512 KiB is not supported");
> + exit(1);
> + }
In case of resend, the RAM size could be tested sooner (after kvm_enabled()).
> + memory_region_add_subregion(get_system_memory(), 0xfff80000, machine->ram);
> +}
> +
> +
> +static void ppe42_machine_class_init(ObjectClass *oc, const void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> + static const char * const valid_cpu_types[] = {
> + POWERPC_CPU_TYPE_NAME("PPE42"),
> + POWERPC_CPU_TYPE_NAME("PPE42X"),
> + POWERPC_CPU_TYPE_NAME("PPE42XM"),
> + NULL,
> + };
> +
> + mc->desc = "PPE42 Test Machine";
> + mc->init = ppe42_machine_init;
> + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("PPE42XM");
> + mc->valid_cpu_types = valid_cpu_types;
> + mc->default_ram_id = "ram";
> + mc->default_ram_size = 512 * KiB;
> +}
> +
> +static const TypeInfo ppe42_machine_info = {
> + .name = TYPE_PPE42_MACHINE,
> + .parent = TYPE_MACHINE,
> + .instance_size = sizeof(Ppe42MachineState),
> + .class_init = ppe42_machine_class_init,
> + .class_size = sizeof(Ppe42MachineClass),
> +};
> +
> +static void ppe42_machine_register_types(void)
> +{
> + type_register_static(&ppe42_machine_info);
> +}
> +
> +type_init(ppe42_machine_register_types);
> +
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
next prev parent reply other threads:[~2025-09-10 7:12 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-08 20:00 [PATCH v3 0/9] Add IBM PPE42 CPU support Glenn Miles
2025-09-08 20:00 ` [PATCH v3 1/9] target/ppc: IBM PPE42 general regs and flags Glenn Miles
2025-09-08 20:00 ` [PATCH v3 2/9] target/ppc: Add IBM PPE42 family of processors Glenn Miles
2025-09-08 20:00 ` [PATCH v3 3/9] target/ppc: IBM PPE42 exception flags and regs Glenn Miles
2025-09-08 20:00 ` [PATCH v3 4/9] target/ppc: Add IBM PPE42 exception model Glenn Miles
2025-09-08 20:00 ` [PATCH v3 5/9] target/ppc: Support for IBM PPE42 MMU Glenn Miles
2025-09-08 20:00 ` [PATCH v3 6/9] target/ppc: Add IBM PPE42 special instructions Glenn Miles
2025-09-12 10:50 ` Chinmay Rath
2025-09-12 15:59 ` Miles Glenn
2025-09-08 20:00 ` [PATCH v3 7/9] hw/ppc: Support for an IBM PPE42 CPU decrementer Glenn Miles
2025-09-08 20:00 ` [PATCH v3 8/9] hw/ppc: Add a test machine for the IBM PPE42 CPU Glenn Miles
2025-09-10 7:10 ` Cédric Le Goater [this message]
2025-09-10 14:21 ` Miles Glenn
2025-09-08 20:00 ` [PATCH v3 9/9] tests/functional: Add test for IBM PPE42 instructions Glenn Miles
2025-09-08 21:17 ` Miles Glenn
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