* [PATCH v2 2/3] hw/ssi: Add Nuvoton PSPI Module
2023-02-07 19:45 [PATCH v2 0/3] Nuvoton Peripheral SPI (PSPI) Module Hao Wu
2023-02-07 19:45 ` [PATCH v2 1/3] MAINTAINERS: Add myself to maintainers and remove Havard Hao Wu
@ 2023-02-07 19:45 ` Hao Wu
2023-02-08 7:48 ` Philippe Mathieu-Daudé
2023-02-07 19:45 ` [PATCH v2 3/3] hw/arm: Attach PSPI module to NPCM7XX SoC Hao Wu
2 siblings, 1 reply; 6+ messages in thread
From: Hao Wu @ 2023-02-07 19:45 UTC (permalink / raw)
To: peter.maydell
Cc: qemu-arm, qemu-devel, wuhaotsh, venture, Avi.Fishman, kfting,
hskinnemoen, titusr, Chris Rauer, Philippe Mathieu-Daude
Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices.
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Chris Rauer <crauer@google.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
---
MAINTAINERS | 6 +-
hw/ssi/meson.build | 2 +-
hw/ssi/npcm_pspi.c | 221 +++++++++++++++++++++++++++++++++++++
hw/ssi/trace-events | 5 +
include/hw/ssi/npcm_pspi.h | 53 +++++++++
5 files changed, 283 insertions(+), 4 deletions(-)
create mode 100644 hw/ssi/npcm_pspi.c
create mode 100644 include/hw/ssi/npcm_pspi.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 347936e41c..1e2a711373 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -803,9 +803,9 @@ M: Tyrone Ting <kfting@nuvoton.com>
M: Hao Wu <wuhaotsh@google.com>
L: qemu-arm@nongnu.org
S: Supported
-F: hw/*/npcm7xx*
-F: include/hw/*/npcm7xx*
-F: tests/qtest/npcm7xx*
+F: hw/*/npcm*
+F: include/hw/*/npcm*
+F: tests/qtest/npcm*
F: pc-bios/npcm7xx_bootrom.bin
F: roms/vbootrom
F: docs/system/arm/nuvoton.rst
diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
index 702aa5e4df..904a47161a 100644
--- a/hw/ssi/meson.build
+++ b/hw/ssi/meson.build
@@ -1,6 +1,6 @@
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c'))
softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c'))
-softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c'))
softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c'))
softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c'))
diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c
new file mode 100644
index 0000000000..1fd865d04e
--- /dev/null
+++ b/hw/ssi/npcm_pspi.c
@@ -0,0 +1,221 @@
+/*
+ * Nuvoton NPCM Peripheral SPI Module (PSPI)
+ *
+ * Copyright 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/irq.h"
+#include "hw/registerfields.h"
+#include "hw/ssi/npcm_pspi.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+
+#include "trace.h"
+
+REG16(PSPI_DATA, 0x0)
+REG16(PSPI_CTL1, 0x2)
+ FIELD(PSPI_CTL1, SPIEN, 0, 1)
+ FIELD(PSPI_CTL1, MOD, 2, 1)
+ FIELD(PSPI_CTL1, EIR, 5, 1)
+ FIELD(PSPI_CTL1, EIW, 6, 1)
+ FIELD(PSPI_CTL1, SCM, 7, 1)
+ FIELD(PSPI_CTL1, SCIDL, 8, 1)
+ FIELD(PSPI_CTL1, SCDV, 9, 7)
+REG16(PSPI_STAT, 0x4)
+ FIELD(PSPI_STAT, BSY, 0, 1)
+ FIELD(PSPI_STAT, RBF, 1, 1)
+
+static void npcm_pspi_update_irq(NPCMPSPIState *s)
+{
+ int level = 0;
+
+ /* Only fire IRQ when the module is enabled. */
+ if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) {
+ /* Update interrupt as BSY is cleared. */
+ if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) &&
+ FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) {
+ level = 1;
+ }
+
+ /* Update interrupt as RBF is set. */
+ if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) &&
+ FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) {
+ level = 1;
+ }
+ }
+ qemu_set_irq(s->irq, level);
+}
+
+static uint16_t npcm_pspi_read_data(NPCMPSPIState *s)
+{
+ uint16_t value = s->regs[R_PSPI_DATA];
+
+ /* Clear stat bits as the value are read out. */
+ s->regs[R_PSPI_STAT] = 0;
+
+ return value;
+}
+
+static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data)
+{
+ uint16_t value = 0;
+
+ if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) {
+ value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8;
+ }
+ value |= ssi_transfer(s->spi, extract16(data, 0, 8));
+ s->regs[R_PSPI_DATA] = value;
+
+ /* Mark data as available */
+ s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK;
+}
+
+/* Control register read handler. */
+static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ NPCMPSPIState *s = opaque;
+ uint16_t value;
+
+ switch (addr) {
+ case A_PSPI_DATA:
+ value = npcm_pspi_read_data(s);
+ break;
+
+ case A_PSPI_CTL1:
+ value = s->regs[R_PSPI_CTL1];
+ break;
+
+ case A_PSPI_STAT:
+ value = s->regs[R_PSPI_STAT];
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: write to invalid offset 0x%" PRIx64 "\n",
+ DEVICE(s)->canonical_path, addr);
+ return 0;
+ }
+ trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value);
+ npcm_pspi_update_irq(s);
+
+ return value;
+}
+
+/* Control register write handler. */
+static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
+ unsigned int size)
+{
+ NPCMPSPIState *s = opaque;
+ uint16_t value = v;
+
+ trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value);
+
+ switch (addr) {
+ case A_PSPI_DATA:
+ npcm_pspi_write_data(s, value);
+ break;
+
+ case A_PSPI_CTL1:
+ s->regs[R_PSPI_CTL1] = value;
+ break;
+
+ case A_PSPI_STAT:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: write to read-only register PSPI_STAT: 0x%08"
+ PRIx64 "\n", DEVICE(s)->canonical_path, v);
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: write to invalid offset 0x%" PRIx64 "\n",
+ DEVICE(s)->canonical_path, addr);
+ return;
+ }
+ npcm_pspi_update_irq(s);
+}
+
+static const MemoryRegionOps npcm_pspi_ctrl_ops = {
+ .read = npcm_pspi_ctrl_read,
+ .write = npcm_pspi_ctrl_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+ .impl = {
+ .min_access_size = 2,
+ .max_access_size = 2,
+ .unaligned = false,
+ },
+};
+
+static void npcm_pspi_enter_reset(Object *obj, ResetType type)
+{
+ NPCMPSPIState *s = NPCM_PSPI(obj);
+
+ trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type);
+ memset(s->regs, 0, sizeof(s->regs));
+}
+
+static void npcm_pspi_realize(DeviceState *dev, Error **errp)
+{
+ NPCMPSPIState *s = NPCM_PSPI(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ Object *obj = OBJECT(dev);
+
+ s->spi = ssi_create_bus(dev, "pspi");
+ memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s,
+ "mmio", 4 * KiB);
+ sysbus_init_mmio(sbd, &s->mmio);
+ sysbus_init_irq(sbd, &s->irq);
+}
+
+static const VMStateDescription vmstate_npcm_pspi = {
+ .name = "npcm-pspi",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
+
+static void npcm_pspi_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "NPCM Peripheral SPI Module";
+ dc->realize = npcm_pspi_realize;
+ dc->vmsd = &vmstate_npcm_pspi;
+ rc->phases.enter = npcm_pspi_enter_reset;
+}
+
+static const TypeInfo npcm_pspi_types[] = {
+ {
+ .name = TYPE_NPCM_PSPI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NPCMPSPIState),
+ .class_init = npcm_pspi_class_init,
+ },
+};
+DEFINE_TYPES(npcm_pspi_types);
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
index c707d4aaba..2d5bd2b83d 100644
--- a/hw/ssi/trace-events
+++ b/hw/ssi/trace-events
@@ -21,6 +21,11 @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset:
npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
+# npcm_pspi.c
+npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d"
+npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
+npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
+
# ibex_spi_host.c
ibex_spi_host_reset(const char *msg) "%s"
diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h
new file mode 100644
index 0000000000..37cc784d96
--- /dev/null
+++ b/include/hw/ssi/npcm_pspi.h
@@ -0,0 +1,53 @@
+/*
+ * Nuvoton Peripheral SPI Module
+ *
+ * Copyright 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM_PSPI_H
+#define NPCM_PSPI_H
+
+#include "hw/ssi/ssi.h"
+#include "hw/sysbus.h"
+
+/*
+ * Number of registers in our device state structure. Don't change this without
+ * incrementing the version_id in the vmstate.
+ */
+#define NPCM_PSPI_NR_REGS 3
+
+/**
+ * NPCMPSPIState - Device state for one Flash Interface Unit.
+ * @parent: System bus device.
+ * @mmio: Memory region for register access.
+ * @spi: The SPI bus mastered by this controller.
+ * @regs: Register contents.
+ * @irq: The interrupt request queue for this module.
+ *
+ * Each PSPI has a shared bank of registers, and controls up to four chip
+ * selects. Each chip select has a dedicated memory region which may be used to
+ * read and write the flash connected to that chip select as if it were memory.
+ */
+typedef struct NPCMPSPIState {
+ SysBusDevice parent;
+
+ MemoryRegion mmio;
+
+ SSIBus *spi;
+ uint16_t regs[NPCM_PSPI_NR_REGS];
+ qemu_irq irq;
+} NPCMPSPIState;
+
+#define TYPE_NPCM_PSPI "npcm-pspi"
+OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI)
+
+#endif /* NPCM_PSPI_H */
--
2.39.1.519.gcb327c4b5f-goog
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 3/3] hw/arm: Attach PSPI module to NPCM7XX SoC
2023-02-07 19:45 [PATCH v2 0/3] Nuvoton Peripheral SPI (PSPI) Module Hao Wu
2023-02-07 19:45 ` [PATCH v2 1/3] MAINTAINERS: Add myself to maintainers and remove Havard Hao Wu
2023-02-07 19:45 ` [PATCH v2 2/3] hw/ssi: Add Nuvoton PSPI Module Hao Wu
@ 2023-02-07 19:45 ` Hao Wu
2 siblings, 0 replies; 6+ messages in thread
From: Hao Wu @ 2023-02-07 19:45 UTC (permalink / raw)
To: peter.maydell
Cc: qemu-arm, qemu-devel, wuhaotsh, venture, Avi.Fishman, kfting,
hskinnemoen, titusr, Philippe Mathieu-Daude
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
---
docs/system/arm/nuvoton.rst | 2 +-
hw/arm/npcm7xx.c | 25 +++++++++++++++++++++++--
include/hw/arm/npcm7xx.h | 2 ++
3 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index c38df32bde..0424cae4b0 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -49,6 +49,7 @@ Supported devices
* SMBus controller (SMBF)
* Ethernet controller (EMC)
* Tachometer
+ * Peripheral SPI controller (PSPI)
Missing devices
---------------
@@ -64,7 +65,6 @@ Missing devices
* Ethernet controller (GMAC)
* USB device (USBD)
- * Peripheral SPI controller (PSPI)
* SD/MMC host
* PECI interface
* PCI and PCIe root complex and bridges
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index d85cc02765..15ff21d047 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -86,6 +86,8 @@ enum NPCM7xxInterrupt {
NPCM7XX_EMC1RX_IRQ = 15,
NPCM7XX_EMC1TX_IRQ,
NPCM7XX_MMC_IRQ = 26,
+ NPCM7XX_PSPI2_IRQ = 28,
+ NPCM7XX_PSPI1_IRQ = 31,
NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
NPCM7XX_TIMER1_IRQ,
NPCM7XX_TIMER2_IRQ,
@@ -220,6 +222,12 @@ static const hwaddr npcm7xx_emc_addr[] = {
0xf0826000,
};
+/* Register base address for each PSPI Module */
+static const hwaddr npcm7xx_pspi_addr[] = {
+ 0xf0200000,
+ 0xf0201000,
+};
+
static const struct {
hwaddr regs_addr;
uint32_t unconnected_pins;
@@ -444,6 +452,10 @@ static void npcm7xx_init(Object *obj)
object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
}
+ for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
+ object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
+ }
+
object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
}
@@ -715,6 +727,17 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
npcm7xx_irq(s, NPCM7XX_MMC_IRQ));
+ /* PSPI */
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi));
+ for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]);
+ int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ;
+
+ sysbus_realize(sbd, &error_abort);
+ sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]);
+ sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq));
+ }
+
create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB);
create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
@@ -724,8 +747,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
- create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB);
- create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB);
create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB);
create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB);
create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB);
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index f1b7e4a48d..72c7722096 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -32,6 +32,7 @@
#include "hw/nvram/npcm7xx_otp.h"
#include "hw/timer/npcm7xx_timer.h"
#include "hw/ssi/npcm7xx_fiu.h"
+#include "hw/ssi/npcm_pspi.h"
#include "hw/usb/hcd-ehci.h"
#include "hw/usb/hcd-ohci.h"
#include "target/arm/cpu.h"
@@ -104,6 +105,7 @@ struct NPCM7xxState {
NPCM7xxFIUState fiu[2];
NPCM7xxEMCState emc[2];
NPCM7xxSDHCIState mmc;
+ NPCMPSPIState pspi[2];
};
#define TYPE_NPCM7XX "npcm7xx"
--
2.39.1.519.gcb327c4b5f-goog
^ permalink raw reply related [flat|nested] 6+ messages in thread