From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 1/2] target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
Date: Fri, 22 Feb 2019 13:55:50 -0800 [thread overview]
Message-ID: <ce67ed48-a67a-de30-944b-a793c46d2a5c@linaro.org> (raw)
In-Reply-To: <20190222170936.13268-2-peter.maydell@linaro.org>
On 2/22/19 9:09 AM, Peter Maydell wrote:
> Instead of gating the A32/T32 FP16 conversion instructions on
> the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of
> looking at ID register bits. In this case MVFR1 fields FPHP
> and SIMDHP indicate the presence of these insns.
>
> This change doesn't alter behaviour for any of our CPUs.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/cpu.h | 37 ++++++++++++++++++++++++++++++++++++-
> target/arm/cpu.c | 2 --
> target/arm/kvm32.c | 3 ---
> target/arm/translate.c | 26 ++++++++++++++++++--------
> 4 files changed, 54 insertions(+), 14 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2019-02-22 21:56 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-22 17:09 [Qemu-devel] [PATCH 0/2] target/arm: Use MVFR feature bits to gate some insns Peter Maydell
2019-02-22 17:09 ` [Qemu-devel] [PATCH 1/2] target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions Peter Maydell
2019-02-22 21:55 ` Richard Henderson [this message]
2019-02-22 17:09 ` [Qemu-devel] [PATCH 2/2] target/arm: Gate "miscellaneous FP" insns by ID register field Peter Maydell
2019-02-22 17:36 ` Peter Maydell
2019-02-22 21:59 ` Richard Henderson
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