From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions
Date: Tue, 13 Oct 2020 10:30:10 -0700 [thread overview]
Message-ID: <ceb80cfb-44ff-cca7-aae7-e4a4dbfabf0d@linaro.org> (raw)
In-Reply-To: <CAFEAcA_EHAsJTDV3JjriUC4rNj829LWCp9PNWScz+7uWFxxCGA@mail.gmail.com>
On 10/13/20 10:12 AM, Peter Maydell wrote:
> On Tue, 13 Oct 2020 at 18:10, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> On 10/12/20 12:56 PM, Peter Maydell wrote:
>>> On Mon, 12 Oct 2020 at 16:37, Peter Maydell <peter.maydell@linaro.org> wrote:
>>> This turns out not to work, because gen_jmp() always generates
>>> a goto-tb for tb exit 0, and we hit the assert() that exit 0
>>> was not used twice. Here's a fixup to fold into this patch:
>>
>> Indeed. I was going to suggest that here you should use arm_gen_condlabel()
>> like you did for LE. Which I think would be still cleaner than your fixup patch.
>
> I thought about that but it doesn't really fit, because
> the condlabel is for "go to the next instruction
> without having done anything". Here we need to do something
> on that codepath (unlike LE).
Ah, right.
Well, the only further comment is that, in the followup, only WLS gains the IT
block check. While I understand that's required to avoid an abort in QEMU for
this case, all three of the insns have that case as CONSTRAINED UNPREDICTABLE.
It might be worthwhile checking for IT in all of them, just to continue our
normal "unpredictable raises sigill, when easy" choice.
r~
next prev parent reply other threads:[~2020-10-13 17:32 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-12 15:37 [PATCH 00/10] target/arm: Various v8.1M minor features Peter Maydell
2020-10-12 15:37 ` [PATCH 01/10] decodetree: Fix codegen for non-overlapping group inside overlapping group Peter Maydell
2020-10-13 16:02 ` Richard Henderson
2020-10-12 15:37 ` [PATCH 02/10] target/arm: Implement v8.1M NOCP handling Peter Maydell
2020-10-12 15:37 ` [PATCH 03/10] target/arm: Implement v8.1M conditional-select insns Peter Maydell
2020-10-13 16:37 ` Richard Henderson
2020-10-12 15:37 ` [PATCH 04/10] target/arm: Make the t32 insn[25:23]=111 group non-overlapping Peter Maydell
2020-10-13 16:40 ` Richard Henderson
2020-10-12 15:37 ` [PATCH 05/10] target/arm: Don't allow BLX imm for M-profile Peter Maydell
2020-10-13 16:41 ` Richard Henderson
2020-10-12 15:37 ` [PATCH 06/10] target/arm: Implement v8.1M branch-future insns (as NOPs) Peter Maydell
2020-10-13 16:58 ` Richard Henderson
2020-10-12 15:37 ` [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions Peter Maydell
2020-10-12 19:56 ` Peter Maydell
2020-10-13 17:10 ` Richard Henderson
2020-10-13 17:12 ` Peter Maydell
2020-10-13 17:30 ` Richard Henderson [this message]
2020-10-13 20:24 ` Peter Maydell
2020-10-13 22:31 ` Richard Henderson
2020-10-12 15:37 ` [PATCH 08/10] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile Peter Maydell
2020-10-13 19:07 ` Richard Henderson
2020-10-12 15:37 ` [PATCH 09/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension Peter Maydell
2020-10-13 20:06 ` Richard Henderson
2020-10-13 20:38 ` Peter Maydell
2020-10-13 21:01 ` Richard Henderson
2020-10-12 15:37 ` [PATCH 10/10] target/arm: Fix writing to FPSCR.FZ16 on M-profile Peter Maydell
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