From: Richard Henderson <richard.henderson@linaro.org>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu
Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 08/28] target/riscv: Convert RV32A insns to decodetree
Date: Sat, 13 Oct 2018 09:50:10 -0700 [thread overview]
Message-ID: <ced866db-2eeb-cf2c-11e9-510b1c0501d9@linaro.org> (raw)
In-Reply-To: <20181012173047.25420-9-kbastian@mail.uni-paderborn.de>
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> @fence .... .... .... ..... ... ..... ....... %pred %succ
> @csr ............ ..... ... ..... ....... %csr %rs1 %rd
>
> +@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=00000 %rs1 %rd
rs2=0. This value is always parsed as decimal, not binary.
> + switch (opc) {
> + case OPC_RISC_AMOSWAP:
> + /* Note that the TCG atomic primitives are SC,
> + so we can ignore AQ/RL along this path. */
> + tcg_gen_atomic_xchg_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOADD:
> + tcg_gen_atomic_fetch_add_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOXOR:
> + tcg_gen_atomic_fetch_xor_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOAND:
> + tcg_gen_atomic_fetch_and_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOOR:
> + tcg_gen_atomic_fetch_or_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOMIN:
> + tcg_gen_atomic_fetch_smin_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOMAX:
> + tcg_gen_atomic_fetch_smax_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOMINU:
> + tcg_gen_atomic_fetch_umin_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOMAXU:
> + tcg_gen_atomic_fetch_umax_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + default:
> + return false;
Given how these switch elements are passed in, this should use
g_assert_not_reached().
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2018-10-13 16:50 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-12 17:30 [Qemu-devel] [PATCH 00/28] target/riscv: Convert to decodetree Bastian Koppelmann
2018-10-12 17:30 ` [Qemu-devel] [PATCH 01/28] targer/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2018-10-12 18:03 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 02/28] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2018-10-12 18:18 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 03/28] target/riscv: Convert RVXI load/store " Bastian Koppelmann
2018-10-12 18:24 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 04/28] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2018-10-12 18:46 ` Richard Henderson
2018-10-19 11:00 ` Bastian Koppelmann
2018-10-19 18:18 ` Palmer Dabbelt
2018-10-12 17:30 ` [Qemu-devel] [PATCH 05/28] target/riscv: Convert RVXI fence " Bastian Koppelmann
2018-10-12 19:17 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 06/28] target/riscv: Convert RVXI csr " Bastian Koppelmann
2018-10-13 16:36 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 07/28] target/riscv: Convert RVXM " Bastian Koppelmann
2018-10-13 16:39 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 08/28] target/riscv: Convert RV32A " Bastian Koppelmann
2018-10-13 16:50 ` Richard Henderson [this message]
2018-10-12 17:30 ` [Qemu-devel] [PATCH 09/28] target/riscv: Convert RV64A " Bastian Koppelmann
2018-10-13 16:51 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 10/28] target/riscv: Convert RV32F " Bastian Koppelmann
2018-10-13 17:33 ` Richard Henderson
2018-10-13 17:41 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 11/28] target/riscv: Convert RV64F " Bastian Koppelmann
2018-10-13 17:37 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 12/28] target/riscv: Convert RV32D " Bastian Koppelmann
2018-10-13 17:42 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 13/28] target/riscv: Convert RV64D " Bastian Koppelmann
2018-10-13 17:44 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 14/28] target/riscv: Convert RV priv " Bastian Koppelmann
2018-10-13 17:52 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 15/28] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2018-10-13 18:18 ` Richard Henderson
2018-10-19 12:49 ` Bastian Koppelmann
2018-10-12 17:30 ` [Qemu-devel] [PATCH 16/28] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2018-10-13 18:53 ` Richard Henderson
2018-10-19 13:20 ` Bastian Koppelmann
2018-10-19 15:28 ` Bastian Koppelmann
2018-10-19 15:38 ` Richard Henderson
2018-10-19 18:49 ` Palmer Dabbelt
2018-10-12 17:30 ` [Qemu-devel] [PATCH 17/28] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2018-10-13 19:34 ` Richard Henderson
2018-10-19 15:10 ` Bastian Koppelmann
2018-10-12 17:30 ` [Qemu-devel] [PATCH 18/28] target/riscv: Remove gen_jalr() Bastian Koppelmann
2018-10-13 19:37 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with trans_branch() Bastian Koppelmann
2018-10-13 19:39 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 20/28] target/riscv: Replace gen_load() with trans_load() Bastian Koppelmann
2018-10-13 19:44 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store() Bastian Koppelmann
2018-10-13 19:45 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 22/28] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2018-10-13 19:54 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2018-10-13 19:55 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 24/28] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2018-10-13 19:57 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 25/28] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2018-10-13 20:00 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 26/28] target/riscv: Remove gen_system() Bastian Koppelmann
2018-10-13 20:00 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 27/28] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2018-10-13 20:01 ` Richard Henderson
2018-10-12 17:30 ` [Qemu-devel] [PATCH 28/28] target/riscv: Replace gen_exception_illegal with return false Bastian Koppelmann
2018-10-13 20:04 ` Richard Henderson
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