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[2603:800c:3202:ffa7:c4c7:6719:c57e:8ffe]) by smtp.gmail.com with ESMTPSA id s125sm3152527pfb.51.2021.07.30.12.07.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 30 Jul 2021 12:07:42 -0700 (PDT) Subject: Re: [PATCH for-6.2 07/53] target/arm: Fix MVE 48-bit SQRSHRL for small right shifts To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210729111512.16541-1-peter.maydell@linaro.org> <20210729111512.16541-8-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Fri, 30 Jul 2021 09:07:39 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210729111512.16541-8-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.125, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/29/21 1:14 AM, Peter Maydell wrote: > We got an edge case wrong in the 48-bit SQRSHRL implementation: if > the shift is to the right, although it always makes the result > smaller than the input value it might not be within the 48-bit range > the result is supposed to be if the input had some bits in [63..48] > set and the shift didn't bring all of those within the [47..0] range. > > Handle this similarly to the way we already do for this case in > do_uqrshl48_d(): extend the calculated result from 48 bits, > and return that if not saturating or if it doesn't change the > result; otherwise fall through to return a saturated value. > > Signed-off-by: Peter Maydell > --- > Not squashed into the previous patch because that one has already > been reviewed, so as this fixes a different edge case I thought > it clearer kept separate. > --- Reviewed-by: Richard Henderson > target/arm/mve_helper.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c > index 5730b48f35e..1a4b2ef8075 100644 > --- a/target/arm/mve_helper.c > +++ b/target/arm/mve_helper.c > @@ -1563,6 +1563,8 @@ uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) > static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, > bool round, uint32_t *sat) > { > + int64_t val, extval; > + > if (shift <= -48) { > /* Rounding the sign bit always produces 0. */ > if (round) { > @@ -1572,9 +1574,14 @@ static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, > } else if (shift < 0) { > if (round) { > src >>= -shift - 1; > - return (src >> 1) + (src & 1); > + val = (src >> 1) + (src & 1); > + } else { > + val = src >> -shift; > + } > + extval = sextract64(val, 0, 48); > + if (!sat || val == extval) { > + return extval; > } > - return src >> -shift; I'll note two things: (1) The val == extval check could be sunk to the end of the function and shared with the left shift, (2) sat will never be unset, as #48 is encoded as sat=1 in the insn. r~