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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f258ccdabsm14396691f8f.28.2025.02.18.01.07.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Feb 2025 01:07:19 -0800 (PST) Message-ID: Date: Tue, 18 Feb 2025 10:07:18 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] hw/timer/hpet: Detect invalid access to TN registers To: Paolo Bonzini , Zhao Liu , "Michael S . Tsirkin" Cc: qemu-devel@nongnu.org References: <20250218073702.3299300-1-zhao1.liu@intel.com> <53739259-69a5-4d7e-9178-f09e1d6ede89@redhat.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <53739259-69a5-4d7e-9178-f09e1d6ede89@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 18/2/25 09:53, Paolo Bonzini wrote: > On 2/18/25 08:37, Zhao Liu wrote: >> "addr & 0x18" ignores invalid address, so that the trace in default >> branch (trace_hpet_ram_{read|write}_invalid()) doesn't work. >> >> Mask addr by "0x1f & ~4", in which 0x1f means to get the complete TN >> registers access and ~4 means to keep any invalid address offset. > > I think this is less readable. > > The reason to use !4 in the Rust code is because the initial AND is done > in a separate function, timer_and_addr(). Having a quick look at the model without looking at the specs: include/hw/timer/hpet.h:20:#define HPET_LEN 0x400 hw/timer/hpet.c:439:static uint64_t hpet_ram_read(..., hw/timer/hpet.c-441-{ hw/timer/hpet.c-448- /*address range of all TN regs*/ hw/timer/hpet.c-449- if (addr >= 0x100 && addr <= 0x3ff) { hw/timer/hpet.c-450- uint8_t timer_id = (addr - 0x100) / 0x20; ... hw/timer/hpet.c-469- } else { hw/timer/hpet.c-470- switch (addr & ~4) { ... hw/timer/hpet.c-488- } hw/timer/hpet.c-489- } hw/timer/hpet.c-490- return 0; hw/timer/hpet.c-491-} hw/timer/hpet.c:699: memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", HPET_LEN); I suppose we want to register multiple timers of I/O size 0x20 at 0x100, and the I/O size of 0x20 at 0x000 is a generic control region. Maybe split hpet_ram_ops in 2 (hpet_cfg_ops and hpet_tmr_ops), mapping the first one once at 0x000 and the other 24 times at 0x100-0x3ff? No clue what is between 0x020-0x0ff. My 2 cents looking at QDev modelling to avoid these address manipulations. Regards, Phil.