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References: <20180208173157.24705-1-alex.bennee@linaro.org>
	<20180208173157.24705-31-alex.bennee@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <cf5584fe-3da6-f4c5-560f-851e2b8f64d5@linaro.org>
Date: Fri, 9 Feb 2018 10:27:09 -0800
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Subject: Re: [Qemu-devel] [PATCH v2 30/32] arm/translate-a64: add all FP16
 ops in simd_scalar_pairwise
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To: =?UTF-8?Q?Alex_Benn=c3=a9e?= <alex.bennee@linaro.org>, qemu-arm@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org

On 02/08/2018 09:31 AM, Alex Bennée wrote:
>      case 0x2f: /* FMINP */
> -        /* FP op, size[0] is 32 or 64 bit */
> +        /* FP op, size[0] is 32 or 64 bit*/

If you're going to frob the whitespace, you might as well update to include the
fact that it can be 16 bit too...

>          if (!u) {
> -            unallocated_encoding(s);
> -            return;
> +            if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
> +                unallocated_encoding(s);
> +                return;
> +            } else {
> +                size = MO_16;
> +            }
> +        } else {
> +            size = extract32(size, 0, 1) ? MO_64 : MO_32;
>          }

Otherwise,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~