From: "Cédric Le Goater" <clg@kaod.org>
To: "Marty E. Plummer" <hanetzer@startmail.com>
Cc: Joel Stanley <joel@jms.id.au>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
David Gibson <david@gibson.dropbear.id.au>
Subject: Re: qemu/powernv: coreboot support?
Date: Tue, 22 Oct 2019 09:58:10 +0200 [thread overview]
Message-ID: <cfc2186f-52e2-53e8-bc3a-9511428542d0@kaod.org> (raw)
In-Reply-To: <20191022003209.6ssq2ojiv57ixeyd@proprietary-killer>
On 22/10/2019 02:32, Marty E. Plummer wrote:
> On Mon, Oct 21, 2019 at 02:46:59PM +0200, Cédric Le Goater wrote:
>> On 21/10/2019 07:34, David Gibson wrote:
>>> On Sun, Oct 20, 2019 at 08:51:47AM +0200, Cédric Le Goater wrote:
>>>> On 20/10/2019 08:28, David Gibson wrote:
>>>>>
>>>>> Ok. Note that the qemu emulated machine doesn't model the hardware
>>>>> right down to the level of hostboot. That's wy we're just loading
>>>>> skiboot and jumping straight into it usually. I guess clg's stuff to
>>>>> load pnor images gets us a little closer to the hardware behaviour,
>>>>> but I think it's still only a rough approximation.
>>>>
> On that note, is qemu-ppc64 currently capable of running LE firmware? My
> coreboot port has currently reached a hitch in that part of the firmware
> headers mapping stuff out is saved in LE mode while the cpu (real or emu)
> is running in BE mode (FMAP headers are saved LE but CBFS headers are
> saved BE)
>>>> It's really tied to the OpenPOWER firmwares using the HIOMAP protocol
>>>> to discuss with the BMC and load the flash. We could loosen how QEMU
>>>> interprets the MTD device and use a property to inform QEMU that this
>>>> is an OpenPOWER PNOR file and that skiboot and can be loaded from it.
>>>> Something to discuss.
>>>
>>> Right. I'm guessing one significant issue here is that to fully model
>>> the BMC, with *its* firmware and comms channels with the main host
>>> would be quite a lot of work, hence cheating a bit to bypass that.
>>
>> In fact, we are not cheating that much. We use the IPMI BT interface of
>> QEMU to handle the HIOMAP communication with the BMC and this model is
>> quite precise.
>>
>> The mapping of the PNOR is simply mapped on the LPC FW address space.
>> The underlying access are simplified because we don't have a LPC model
>> but we could generate all the SPI transaction using the Aspeed models.
>> I had experiments in that sense for P8.
>>
> Honestly getting the coreboot.rom into the lpc fw addr space in the same
> way you do pnor images would be a useful sim, as that's more or less how
> its going to be done on existing hardware.
That is covered by patch 'ppc/pnv: Add HIOMAP commands' in the series
I sent.
C.
next prev parent reply other threads:[~2019-10-22 8:08 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-18 17:28 qemu/powernv: coreboot support? Marty E. Plummer
2019-10-19 11:15 ` David Gibson
2019-10-19 12:28 ` Marty E. Plummer
2019-10-19 13:46 ` Cédric Le Goater
2019-10-19 15:31 ` Marty E. Plummer
2019-10-19 15:53 ` Cédric Le Goater
2019-10-19 16:09 ` Marty E. Plummer
2019-10-20 6:28 ` David Gibson
2019-10-20 6:51 ` Cédric Le Goater
2019-10-20 16:32 ` Marty E. Plummer
2019-10-21 5:34 ` David Gibson
2019-10-21 12:46 ` Cédric Le Goater
2019-10-22 0:32 ` Marty E. Plummer
2019-10-22 1:40 ` David Gibson
2019-10-22 2:17 ` Marty E. Plummer
2019-10-22 7:55 ` David Gibson
2019-10-22 7:58 ` Cédric Le Goater [this message]
2019-10-23 21:41 ` Marty E. Plummer
2019-10-19 18:51 ` Marty E. Plummer
2019-10-19 19:23 ` Marty E. Plummer
2019-10-20 19:48 ` Peter Maydell
2019-10-21 9:51 ` Philippe Mathieu-Daudé
2019-10-20 6:26 ` David Gibson
2019-10-20 6:24 ` David Gibson
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