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[2403:580a:f89b:0:e01b:92e5:d779:1bc0]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ff592ad853sm94050835ad.280.2024.08.06.19.01.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 06 Aug 2024 19:01:29 -0700 (PDT) Message-ID: Date: Wed, 7 Aug 2024 12:01:21 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 07/20] target/riscv: zicfilp `lpad` impl and branch tracking To: Deepak Gupta , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: pbonzini@redhat.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Jim Shu , Andy Chiu References: <20240807000652.1417776-1-debug@rivosinc.com> <20240807000652.1417776-8-debug@rivosinc.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240807000652.1417776-8-debug@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/7/24 10:06, Deepak Gupta wrote: > diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h > index 02afad608b..e6927ff847 100644 > --- a/target/riscv/cpu_user.h > +++ b/target/riscv/cpu_user.h > @@ -15,5 +15,6 @@ > #define xA6 16 > #define xA7 17 /* syscall number for RVI ABI */ > #define xT0 5 /* syscall number for RVE ABI */ > +#define xT2 7 Maybe just add them all? > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc > index 98e3806d5e..cbd7d5c395 100644 > --- a/target/riscv/insn_trans/trans_rvi.c.inc > +++ b/target/riscv/insn_trans/trans_rvi.c.inc > @@ -36,6 +36,58 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a) > return true; > } > > +static bool trans_lpad(DisasContext *ctx, arg_lpad *a) > +{ > + bool lp_expected; > + /* zicfilp only supported on 32bit and 64bit */ > + if (get_xl(ctx) != MXL_RV32 && get_xl(ctx) != MXL_RV64) { > + return false; > + } Where does it say that? There doesn't seem to be anything in the spec that excludes rv128. > + lp_expected = ctx->fcfi_lp_expected; > + /* forward cfi not enabled or lp not expected, return false */ > + if (!ctx->fcfi_enabled) { > + return false; > + } Comments should explain why, not exactly mirror the code. In any case, better as: /* * If zicfilp not present, the encoding is a nop. * If forward cfi not enabled, the implementation is a nop. */ if (!ctx->fcfi_enabled) { return true; } No need to fall through into AUIPC to re-discover nop-ness. > + > + /* > + * If this is the first instruction of the TB, let the translator > + * know the landing pad requirement was satisfied. No need to bother > + * checking for CFI feature or enablement. > + */ Comment is strange, because you have just checked enablement. > + /* if lp was expected, do label check */ > + if (lp_expected) { > + TCGLabel *skip = gen_new_label(); > + TCGv tmp = tcg_temp_new(); > + tcg_gen_st_tl(tcg_constant_tl(NO_LP_EXPECTED), > + tcg_env, offsetof(CPURISCVState, elp)); This placement is wrong, according to the LPAD pseudocode. It must go last. > + tcg_gen_extract_tl(tmp, get_gpr(ctx, xT2, EXT_NONE), 12, 20); > + tcg_gen_brcondi_tl(TCG_COND_EQ, tcg_constant_tl(a->imm_cfi20), 0, skip); This one you check at translation time: if (a->imm_cfi20 != 0) > + tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, a->imm_cfi20, skip); > + gen_helper_raise_sw_check_excep(tcg_env, > + tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), > + tcg_constant_tl(LABEL_MISMATCH_LPAD), tcg_constant_tl(0)); > + gen_set_label(skip); > + } > + > + return true; > +} > + > static bool trans_auipc(DisasContext *ctx, arg_auipc *a) > { > TCGv target_pc = dest_gpr(ctx, a->rd); > @@ -75,6 +127,20 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) > gen_set_gpr(ctx, a->rd, succ_pc); > > tcg_gen_mov_tl(cpu_pc, target_pc); > + if (ctx->cfg_ptr->ext_zicfilp && ctx->fcfi_enabled) { No need to check ext_zicfilp, as fcfi_enabled includes that already. > + /* > + * Rely on a helper to check the forward CFI enable for the > + * current process mode. The alternatives would be (1) include > + * "fcfi enabled" in the cflags or (2) maintain a "fcfi > + * currently enabled" in tcg_env and emit TCG code to access > + * and test it. > + */ Comment is out of date. > + if (a->rs1 != xRA && a->rs1 != xT0 && a->rs1 != xT2) { > + tcg_gen_st_tl(tcg_constant_tl(LP_EXPECTED), > + tcg_env, offsetof(CPURISCVState, elp)); > + } > + } > + > lookup_and_goto_ptr(ctx); > > if (misaligned) { r~