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From: Richard Henderson <richard.henderson@linaro.org>
To: "Lucas Mateus Castro(alqotel)" <lucas.araujo@eldorado.org.br>,
	qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: Greg Kurz <groug@kaod.org>,
	danielhb413@gmail.com, clg@kaod.org,
	David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [PATCH 03/10] target/ppc: Implemented vector divide instructions
Date: Wed, 30 Mar 2022 15:06:31 -0600	[thread overview]
Message-ID: <cffe9d6a-b268-81ad-bccb-ffe0c7bde8bd@linaro.org> (raw)
In-Reply-To: <20220330202515.66554-4-lucas.araujo@eldorado.org.br>

On 3/30/22 14:25, Lucas Mateus Castro(alqotel) wrote:
> +#define TRANS_VDIV_VMOD(FLAGS, NAME, VECE, FNI4_FUNC, FNI8_FUNC)        \
> +static bool trans_##NAME(DisasContext *ctx, arg_VX *a)                  \
> +{                                                                       \
> +    static const GVecGen3 op[2] = {                                     \
> +        {                                                               \
> +            .fni4 = FNI4_FUNC,                                          \
> +            .fni8 = FNI8_FUNC,                                          \
> +            .vece = MO_32                                               \
> +        },                                                              \
> +        {                                                               \
> +            .fni4 = FNI4_FUNC,                                          \
> +            .fni8 = FNI8_FUNC,                                          \
> +            .vece = MO_64                                               \
> +        },                                                              \
> +    };                                                                  \

There is zero point in having a two element array here:
(1) VECE is a constant
(2) The unused array element is actively wrong.

> +#define DIV_VEC(NAME, SZ, DIV)                                          \
> +static void do_vx_##NAME(TCGv_##SZ t, TCGv_##SZ a, TCGv_##SZ b)         \
> +{                                                                       \
> +    TCGv_##SZ zero = tcg_constant_##SZ(0), one = tcg_constant_##SZ(1);  \
> +    /*                                                                  \
> +     *  If N/0 the instruction used by the backend might deliver        \
> +     *  a signal to the process and the hardware returns 0 when         \
> +     *  N/0, so if b = 0 return 0/1                                     \
> +     */                                                                 \
> +    tcg_gen_movcond_##SZ(TCG_COND_EQ, a, b, zero, zero, a);             \
> +    tcg_gen_movcond_##SZ(TCG_COND_EQ, b, b, zero, one, b);              \
> +    DIV(t, a, b);                                                       \
> +}

The manual says N/0 = undefined.  I don't think it's important to require 0.

The signed versions still need to check for int_min / -1, which will fault on x86. 
Compare vs gen_op_arith_div{w,d}.


r~


  reply	other threads:[~2022-03-30 21:08 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-30 20:25 [PATCH 00/10] VDIV/VMOD Implementation Lucas Mateus Castro(alqotel)
2022-03-30 20:25 ` [PATCH 01/10] qemu/int128: avoid undefined behavior in int128_lshift Lucas Mateus Castro(alqotel)
2022-03-30 21:21   ` Peter Maydell
2022-03-30 20:25 ` [PATCH 02/10] qemu/int128: add int128_urshift Lucas Mateus Castro(alqotel)
2022-03-30 20:25 ` [PATCH 03/10] target/ppc: Implemented vector divide instructions Lucas Mateus Castro(alqotel)
2022-03-30 21:06   ` Richard Henderson [this message]
2022-03-31 18:28     ` Lucas Mateus Martins Araujo e Castro
2022-03-30 20:25 ` [PATCH 04/10] target/ppc: Implemented vector divide quadword Lucas Mateus Castro(alqotel)
2022-03-30 20:25 ` [PATCH 05/10] target/ppc: Implemented vector divide extended word Lucas Mateus Castro(alqotel)
2022-03-30 21:24   ` Richard Henderson
2022-03-30 20:25 ` [PATCH 06/10] Implemented unsigned 256-by-128 division Lucas Mateus Castro(alqotel)
2022-03-30 20:25 ` [PATCH 07/10] Implemented signed " Lucas Mateus Castro(alqotel)
2022-03-30 21:45   ` Richard Henderson
2022-03-30 20:25 ` [PATCH 08/10] target/ppc: Implemented remaining vector divide extended Lucas Mateus Castro(alqotel)
2022-03-30 20:25 ` [PATCH 09/10] target/ppc: Implemented vector module word/doubleword Lucas Mateus Castro(alqotel)
2022-03-30 20:25 ` [PATCH 10/10] target/ppc: Implemented vector module quadword Lucas Mateus Castro(alqotel)

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