From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Subject: Re: [PATCH] target/arm: Correct ID_AA64ISAR1_EL1 value for neoverse-v1
Date: Wed, 18 Sep 2024 16:22:47 +0200 [thread overview]
Message-ID: <cfffe21e-258e-4592-802e-0797a045b97f@linaro.org> (raw)
In-Reply-To: <20240917161337.3012188-1-peter.maydell@linaro.org>
On 9/17/24 18:13, Peter Maydell wrote:
> The Neoverse-V1 TRM is a bit confused about the layout of the
> ID_AA64ISAR1_EL1 register, and so its table 3-6 has the wrong value
> for this ID register. Trust instead section 3.2.74's list of which
> fields are set.
>
> This means that we stop incorrectly reporting FEAT_XS as present, and
> now report the presence of FEAT_BF16.
>
> Cc:qemu-stable@nongnu.org
> Reported-by: Marcin Juszkiewicz<marcin.juszkiewicz@linaro.org>
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
> target/arm/tcg/cpu64.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2024-09-19 10:05 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-17 16:13 [PATCH] target/arm: Correct ID_AA64ISAR1_EL1 value for neoverse-v1 Peter Maydell
2024-09-18 14:22 ` Richard Henderson [this message]
2024-09-20 8:10 ` Marcin Juszkiewicz
2024-09-20 8:11 ` Michael Tokarev
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