* [Qemu-devel] [PATCH 01/13] piix4 don't use pci_irq_levels at all
2009-08-27 23:15 [Qemu-devel] [PATCH 00/13] piix_pci cleanup Juan Quintela
@ 2009-08-27 23:15 ` Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 02/13] Split piix4 support from piix_pci.c Juan Quintela
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Juan Quintela @ 2009-08-27 23:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/piix_pci.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index e2ddf4b..7cf1d99 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -321,8 +321,6 @@ static void piix4_reset(void *opaque)
pci_conf[0xab] = 0x00;
pci_conf[0xac] = 0x00;
pci_conf[0xae] = 0x00;
-
- memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
}
static void piix_save(QEMUFile* f, void *opaque)
--
1.6.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH 02/13] Split piix4 support from piix_pci.c
2009-08-27 23:15 [Qemu-devel] [PATCH 00/13] piix_pci cleanup Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 01/13] piix4 don't use pci_irq_levels at all Juan Quintela
@ 2009-08-27 23:15 ` Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 03/13] low_set_irq is not used anywhere Juan Quintela
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Juan Quintela @ 2009-08-27 23:15 UTC (permalink / raw)
To: qemu-devel
Now mips_malta uses piix4 and pc's use piix_pci definitions
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
Makefile.target | 2 +-
hw/pc.h | 1 +
hw/piix4.c | 127 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/piix_pci.c | 71 -------------------------------
4 files changed, 129 insertions(+), 72 deletions(-)
create mode 100644 hw/piix4.c
diff --git a/Makefile.target b/Makefile.target
index 0f8137b..9363ffa 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -212,7 +212,7 @@ obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
obj-mips-y += mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o rc4030.o
obj-mips-y += g364fb.o jazz_led.o dp8393x.o
obj-mips-y += ide.o gt64xxx.o pckbd.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o
-obj-mips-y += piix_pci.o parallel.o cirrus_vga.o isa-bus.o pcspk.o $(sound-obj-y)
+obj-mips-y += piix4.o parallel.o cirrus_vga.o isa-bus.o pcspk.o $(sound-obj-y)
obj-mips-y += mipsnet.o
obj-mips-y += pflash_cfi01.o
obj-mips-y += vmware_vga.o
diff --git a/hw/pc.h b/hw/pc.h
index 5649fc4..f76e118 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -122,6 +122,7 @@ void i440fx_set_smm(PCIDevice *d, int val);
int piix3_init(PCIBus *bus, int devfn);
void i440fx_init_memory_mappings(PCIDevice *d);
+/* piix4.c */
extern PCIDevice *piix4_dev;
int piix4_init(PCIBus *bus, int devfn);
diff --git a/hw/piix4.c b/hw/piix4.c
new file mode 100644
index 0000000..c489f13
--- /dev/null
+++ b/hw/piix4.c
@@ -0,0 +1,127 @@
+/*
+ * QEMU PIIX4 PCI Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw.h"
+#include "pc.h"
+#include "pci.h"
+#include "isa.h"
+#include "sysbus.h"
+
+PCIDevice *piix4_dev;
+
+static void piix4_reset(void *opaque)
+{
+ PCIDevice *d = opaque;
+ uint8_t *pci_conf = d->config;
+
+ pci_conf[0x04] = 0x07; // master, memory and I/O
+ pci_conf[0x05] = 0x00;
+ pci_conf[0x06] = 0x00;
+ pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
+ pci_conf[0x4c] = 0x4d;
+ pci_conf[0x4e] = 0x03;
+ pci_conf[0x4f] = 0x00;
+ pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
+ pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
+ pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
+ pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
+ pci_conf[0x69] = 0x02;
+ pci_conf[0x70] = 0x80;
+ pci_conf[0x76] = 0x0c;
+ pci_conf[0x77] = 0x0c;
+ pci_conf[0x78] = 0x02;
+ pci_conf[0x79] = 0x00;
+ pci_conf[0x80] = 0x00;
+ pci_conf[0x82] = 0x00;
+ pci_conf[0xa0] = 0x08;
+ pci_conf[0xa2] = 0x00;
+ pci_conf[0xa3] = 0x00;
+ pci_conf[0xa4] = 0x00;
+ pci_conf[0xa5] = 0x00;
+ pci_conf[0xa6] = 0x00;
+ pci_conf[0xa7] = 0x00;
+ pci_conf[0xa8] = 0x0f;
+ pci_conf[0xaa] = 0x00;
+ pci_conf[0xab] = 0x00;
+ pci_conf[0xac] = 0x00;
+ pci_conf[0xae] = 0x00;
+}
+
+static void piix_save(QEMUFile* f, void *opaque)
+{
+ PCIDevice *d = opaque;
+ pci_device_save(d, f);
+}
+
+static int piix_load(QEMUFile* f, void *opaque, int version_id)
+{
+ PCIDevice *d = opaque;
+ if (version_id != 2)
+ return -EINVAL;
+ return pci_device_load(d, f);
+}
+
+static void piix4_initfn(PCIDevice *d)
+{
+ uint8_t *pci_conf;
+
+ register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
+
+ pci_conf = d->config;
+ pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
+ pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
+ pci_conf[PCI_HEADER_TYPE] =
+ PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
+
+ piix4_dev = d;
+ piix4_reset(d);
+ qemu_register_reset(piix4_reset, d);
+}
+
+int piix4_init(PCIBus *bus, int devfn)
+{
+ PCIDevice *d;
+
+ d = pci_create_simple(bus, devfn, "PIIX4");
+ return d->devfn;
+}
+
+static PCIDeviceInfo piix4_info[] = {
+ {
+ .qdev.name = "PIIX4",
+ .qdev.desc = "ISA bridge",
+ .qdev.size = sizeof(PCIDevice),
+ .qdev.no_user = 1,
+ .init = piix4_initfn,
+ },{
+ /* end of list */
+ }
+};
+
+static void piix4_register(void)
+{
+ pci_qdev_register_many(piix4_info);
+}
+device_init(piix4_register);
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 7cf1d99..86db2fc 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -222,7 +222,6 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
/* PIIX3 PCI to ISA bridge */
static PCIDevice *piix3_dev;
-PCIDevice *piix4_dev;
static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
{
@@ -285,44 +284,6 @@ static void piix3_reset(void *opaque)
memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
}
-static void piix4_reset(void *opaque)
-{
- PCIDevice *d = opaque;
- uint8_t *pci_conf = d->config;
-
- pci_conf[0x04] = 0x07; // master, memory and I/O
- pci_conf[0x05] = 0x00;
- pci_conf[0x06] = 0x00;
- pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
- pci_conf[0x4c] = 0x4d;
- pci_conf[0x4e] = 0x03;
- pci_conf[0x4f] = 0x00;
- pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
- pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
- pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
- pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
- pci_conf[0x69] = 0x02;
- pci_conf[0x70] = 0x80;
- pci_conf[0x76] = 0x0c;
- pci_conf[0x77] = 0x0c;
- pci_conf[0x78] = 0x02;
- pci_conf[0x79] = 0x00;
- pci_conf[0x80] = 0x00;
- pci_conf[0x82] = 0x00;
- pci_conf[0xa0] = 0x08;
- pci_conf[0xa2] = 0x00;
- pci_conf[0xa3] = 0x00;
- pci_conf[0xa4] = 0x00;
- pci_conf[0xa5] = 0x00;
- pci_conf[0xa6] = 0x00;
- pci_conf[0xa7] = 0x00;
- pci_conf[0xa8] = 0x0f;
- pci_conf[0xaa] = 0x00;
- pci_conf[0xab] = 0x00;
- pci_conf[0xac] = 0x00;
- pci_conf[0xae] = 0x00;
-}
-
static void piix_save(QEMUFile* f, void *opaque)
{
PCIDevice *d = opaque;
@@ -356,24 +317,6 @@ static void piix3_initfn(PCIDevice *d)
qemu_register_reset(piix3_reset, d);
}
-static void piix4_initfn(PCIDevice *d)
-{
- uint8_t *pci_conf;
-
- register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
-
- pci_conf = d->config;
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
- pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
- pci_conf[PCI_HEADER_TYPE] =
- PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
-
- piix4_dev = d;
- piix4_reset(d);
- qemu_register_reset(piix4_reset, d);
-}
-
int piix3_init(PCIBus *bus, int devfn)
{
PCIDevice *d;
@@ -382,14 +325,6 @@ int piix3_init(PCIBus *bus, int devfn)
return d->devfn;
}
-int piix4_init(PCIBus *bus, int devfn)
-{
- PCIDevice *d;
-
- d = pci_create_simple(bus, devfn, "PIIX4");
- return d->devfn;
-}
-
static PCIDeviceInfo i440fx_info[] = {
{
.qdev.name = "i440FX",
@@ -405,12 +340,6 @@ static PCIDeviceInfo i440fx_info[] = {
.qdev.no_user = 1,
.init = piix3_initfn,
},{
- .qdev.name = "PIIX4",
- .qdev.desc = "ISA bridge",
- .qdev.size = sizeof(PCIDevice),
- .qdev.no_user = 1,
- .init = piix4_initfn,
- },{
/* end of list */
}
};
--
1.6.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH 03/13] low_set_irq is not used anywhere
2009-08-27 23:15 [Qemu-devel] [PATCH 00/13] piix_pci cleanup Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 01/13] piix4 don't use pci_irq_levels at all Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 02/13] Split piix4 support from piix_pci.c Juan Quintela
@ 2009-08-27 23:15 ` Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 04/13] Use PCII440FXState instead of generic PCIDevice Juan Quintela
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Juan Quintela @ 2009-08-27 23:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/pci.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 27eac04..e209ceb 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -41,8 +41,6 @@ struct PCIBus {
pci_set_irq_fn set_irq;
pci_map_irq_fn map_irq;
uint32_t config_reg; /* XXX: suppress */
- /* low level pic */
- SetIRQFunc *low_set_irq;
qemu_irq *irq_opaque;
PCIDevice *devices[256];
PCIDevice *parent_dev;
--
1.6.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH 04/13] Use PCII440FXState instead of generic PCIDevice
2009-08-27 23:15 [Qemu-devel] [PATCH 00/13] piix_pci cleanup Juan Quintela
` (2 preceding siblings ...)
2009-08-27 23:15 ` [Qemu-devel] [PATCH 03/13] low_set_irq is not used anywhere Juan Quintela
@ 2009-08-27 23:15 ` Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 05/13] Move smm_enabled and isa_memory_mappings to PCII440FXState Juan Quintela
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Juan Quintela @ 2009-08-27 23:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/pc.c | 2 +-
hw/pc.h | 9 ++++++---
hw/piix_pci.c | 54 +++++++++++++++++++++++++++++++-----------------------
3 files changed, 38 insertions(+), 27 deletions(-)
diff --git a/hw/pc.c b/hw/pc.c
index 11b8618..b240ae5 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -61,7 +61,7 @@
static fdctrl_t *floppy_controller;
static RTCState *rtc_state;
static PITState *pit;
-static PCIDevice *i440fx_state;
+static PCII440FXState *i440fx_state;
typedef struct rom_reset_data {
uint8_t *data;
diff --git a/hw/pc.h b/hw/pc.h
index f76e118..3604c70 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -117,10 +117,13 @@ void pcspk_init(PITState *);
int pcspk_audio_init(qemu_irq *pic);
/* piix_pci.c */
-PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
-void i440fx_set_smm(PCIDevice *d, int val);
+struct PCII440FXState;
+typedef struct PCII440FXState PCII440FXState;
+
+PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic);
+void i440fx_set_smm(PCII440FXState *d, int val);
int piix3_init(PCIBus *bus, int devfn);
-void i440fx_init_memory_mappings(PCIDevice *d);
+void i440fx_init_memory_mappings(PCII440FXState *d);
/* piix4.c */
extern PCIDevice *piix4_dev;
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 86db2fc..2450c31 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -33,6 +33,10 @@ typedef uint32_t pci_addr_t;
typedef PCIHostState I440FXState;
+struct PCII440FXState {
+ PCIDevice dev;
+};
+
static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
{
I440FXState *s = opaque;
@@ -61,7 +65,7 @@ static target_phys_addr_t isa_page_descs[384 / 4];
static uint8_t smm_enabled;
static int pci_irq_levels[4];
-static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
+static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
{
uint32_t addr;
@@ -88,17 +92,17 @@ static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
}
}
-static void i440fx_update_memory_mappings(PCIDevice *d)
+static void i440fx_update_memory_mappings(PCII440FXState *d)
{
int i, r;
uint32_t smram, addr;
- update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3);
+ update_pam(d, 0xf0000, 0x100000, (d->dev.config[0x59] >> 4) & 3);
for(i = 0; i < 12; i++) {
- r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
+ r = (d->dev.config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
}
- smram = d->config[0x72];
+ smram = d->dev.config[0x72];
if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
} else {
@@ -109,7 +113,7 @@ static void i440fx_update_memory_mappings(PCIDevice *d)
}
}
-void i440fx_set_smm(PCIDevice *d, int val)
+void i440fx_set_smm(PCII440FXState *d, int val)
{
val = (val != 0);
if (smm_enabled != val) {
@@ -122,7 +126,7 @@ void i440fx_set_smm(PCIDevice *d, int val)
/* XXX: suppress when better memory API. We make the assumption that
no device (in particular the VGA) changes the memory mappings in
the 0xa0000-0x100000 range */
-void i440fx_init_memory_mappings(PCIDevice *d)
+void i440fx_init_memory_mappings(PCII440FXState *d)
{
int i;
for(i = 0; i < 96; i++) {
@@ -130,21 +134,23 @@ void i440fx_init_memory_mappings(PCIDevice *d)
}
}
-static void i440fx_write_config(PCIDevice *d,
+static void i440fx_write_config(PCIDevice *dev,
uint32_t address, uint32_t val, int len)
{
+ PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
+
/* XXX: implement SMRAM.D_LOCK */
- pci_default_write_config(d, address, val, len);
+ pci_default_write_config(dev, address, val, len);
if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
i440fx_update_memory_mappings(d);
}
static void i440fx_save(QEMUFile* f, void *opaque)
{
- PCIDevice *d = opaque;
+ PCII440FXState *d = opaque;
int i;
- pci_device_save(d, f);
+ pci_device_save(&d->dev, f);
qemu_put_8s(f, &smm_enabled);
for (i = 0; i < 4; i++)
@@ -153,12 +159,12 @@ static void i440fx_save(QEMUFile* f, void *opaque)
static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
{
- PCIDevice *d = opaque;
+ PCII440FXState *d = opaque;
int ret, i;
if (version_id > 2)
return -EINVAL;
- ret = pci_device_load(d, f);
+ ret = pci_device_load(&d->dev, f);
if (ret < 0)
return ret;
i440fx_update_memory_mappings(d);
@@ -186,20 +192,22 @@ static void i440fx_pcihost_initfn(SysBusDevice *dev)
register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
}
-static void i440fx_initfn(PCIDevice *d)
+static void i440fx_initfn(PCIDevice *dev)
{
- pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
- pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_82441);
- d->config[0x08] = 0x02; // revision
- pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
- d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
+ PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
- d->config[0x72] = 0x02; /* SMRAM */
+ pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
+ d->dev.config[0x08] = 0x02; // revision
+ pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
+ d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
+
+ d->dev.config[0x72] = 0x02; /* SMRAM */
register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
}
-PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
+PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic)
{
DeviceState *dev;
PCIBus *b;
@@ -214,7 +222,7 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
qdev_init(dev);
d = pci_create_simple(b, 0, "i440FX");
- *pi440fx_state = d;
+ *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
return b;
}
@@ -329,7 +337,7 @@ static PCIDeviceInfo i440fx_info[] = {
{
.qdev.name = "i440FX",
.qdev.desc = "Host bridge",
- .qdev.size = sizeof(PCIDevice),
+ .qdev.size = sizeof(PCII440FXState),
.qdev.no_user = 1,
.init = i440fx_initfn,
.config_write = i440fx_write_config,
--
1.6.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH 05/13] Move smm_enabled and isa_memory_mappings to PCII440FXState
2009-08-27 23:15 [Qemu-devel] [PATCH 00/13] piix_pci cleanup Juan Quintela
` (3 preceding siblings ...)
2009-08-27 23:15 ` [Qemu-devel] [PATCH 04/13] Use PCII440FXState instead of generic PCIDevice Juan Quintela
@ 2009-08-27 23:15 ` Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 06/13] We want the argument pass to set_irq to be opaque Juan Quintela
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Juan Quintela @ 2009-08-27 23:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/piix_pci.c | 20 ++++++++++----------
1 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 2450c31..d8aeeec 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -35,6 +35,8 @@ typedef PCIHostState I440FXState;
struct PCII440FXState {
PCIDevice dev;
+ target_phys_addr_t isa_page_descs[384 / 4];
+ uint8_t smm_enabled;
};
static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
@@ -61,8 +63,6 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
return (irq_num + slot_addend) & 3;
}
-static target_phys_addr_t isa_page_descs[384 / 4];
-static uint8_t smm_enabled;
static int pci_irq_levels[4];
static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
@@ -86,7 +86,7 @@ static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
/* XXX: should distinguish read/write cases */
for(addr = start; addr < end; addr += 4096) {
cpu_register_physical_memory(addr, 4096,
- isa_page_descs[(addr - 0xa0000) >> 12]);
+ d->isa_page_descs[(addr - 0xa0000) >> 12]);
}
break;
}
@@ -103,12 +103,12 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
}
smram = d->dev.config[0x72];
- if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
+ if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
} else {
for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
cpu_register_physical_memory(addr, 4096,
- isa_page_descs[(addr - 0xa0000) >> 12]);
+ d->isa_page_descs[(addr - 0xa0000) >> 12]);
}
}
}
@@ -116,8 +116,8 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
void i440fx_set_smm(PCII440FXState *d, int val)
{
val = (val != 0);
- if (smm_enabled != val) {
- smm_enabled = val;
+ if (d->smm_enabled != val) {
+ d->smm_enabled = val;
i440fx_update_memory_mappings(d);
}
}
@@ -130,7 +130,7 @@ void i440fx_init_memory_mappings(PCII440FXState *d)
{
int i;
for(i = 0; i < 96; i++) {
- isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
+ d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
}
}
@@ -151,7 +151,7 @@ static void i440fx_save(QEMUFile* f, void *opaque)
int i;
pci_device_save(&d->dev, f);
- qemu_put_8s(f, &smm_enabled);
+ qemu_put_8s(f, &d->smm_enabled);
for (i = 0; i < 4; i++)
qemu_put_be32(f, pci_irq_levels[i]);
@@ -168,7 +168,7 @@ static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
if (ret < 0)
return ret;
i440fx_update_memory_mappings(d);
- qemu_get_8s(f, &smm_enabled);
+ qemu_get_8s(f, &d->smm_enabled);
if (version_id >= 2)
for (i = 0; i < 4; i++)
--
1.6.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH 06/13] We want the argument pass to set_irq to be opaque
2009-08-27 23:15 [Qemu-devel] [PATCH 00/13] piix_pci cleanup Juan Quintela
` (4 preceding siblings ...)
2009-08-27 23:15 ` [Qemu-devel] [PATCH 05/13] Move smm_enabled and isa_memory_mappings to PCII440FXState Juan Quintela
@ 2009-08-27 23:15 ` Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 07/13] Create PIIX3State instead of using PCIDevice for PIIX3 Juan Quintela
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Juan Quintela @ 2009-08-27 23:15 UTC (permalink / raw)
To: qemu-devel
piix_pci want to pass more things that the pic
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/apb_pci.c | 4 +++-
hw/grackle_pci.c | 4 +++-
hw/gt64xxx.c | 3 ++-
hw/pci.c | 6 +++---
hw/pci.h | 6 +++---
hw/piix_pci.c | 5 +++--
hw/ppc4xx_pci.c | 4 +++-
hw/ppce500_pci.c | 4 +++-
hw/prep_pci.c | 4 +++-
hw/r2d.c | 4 +++-
hw/sh_pci.c | 4 ++--
hw/unin_pci.c | 4 +++-
hw/versatile_pci.c | 4 +++-
13 files changed, 37 insertions(+), 19 deletions(-)
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 13284c6..a46d7a6 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -218,8 +218,10 @@ static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
return bus_offset + irq_num;
}
-static void pci_apb_set_irq(qemu_irq *pic, int irq_num, int level)
+static void pci_apb_set_irq(void *opaque, int irq_num, int level)
{
+ qemu_irq *pic = opaque;
+
/* PCI IRQ map onto the first 32 INO. */
qemu_set_irq(pic[irq_num], level);
}
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index 5b6778e..db6a216 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -102,8 +102,10 @@ static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
return (irq_num + (pci_dev->devfn >> 3)) & 3;
}
-static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level)
+static void pci_grackle_set_irq(void *opaque, int irq_num, int level)
{
+ qemu_irq *pic = opaque;
+
GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
qemu_set_irq(pic[irq_num + 0x15], level);
}
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 2115130..8f9ae4a 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -893,9 +893,10 @@ static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
static int pci_irq_levels[4];
-static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level)
+static void pci_gt64120_set_irq(void *opaque, int irq_num, int level)
{
int i, pic_irq, pic_level;
+ qemu_irq *pic = opaque;
pci_irq_levels[irq_num] = level;
diff --git a/hw/pci.c b/hw/pci.c
index e209ceb..c37a732 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -41,7 +41,7 @@ struct PCIBus {
pci_set_irq_fn set_irq;
pci_map_irq_fn map_irq;
uint32_t config_reg; /* XXX: suppress */
- qemu_irq *irq_opaque;
+ void *irq_opaque;
PCIDevice *devices[256];
PCIDevice *parent_dev;
PCIBus *next;
@@ -119,7 +119,7 @@ static void pci_bus_reset(void *opaque)
PCIBus *pci_register_bus(DeviceState *parent, const char *name,
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
- qemu_irq *pic, int devfn_min, int nirq)
+ void *irq_opaque, int devfn_min, int nirq)
{
PCIBus *bus;
static int nbus = 0;
@@ -127,7 +127,7 @@ PCIBus *pci_register_bus(DeviceState *parent, const char *name,
bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name));
bus->set_irq = set_irq;
bus->map_irq = map_irq;
- bus->irq_opaque = pic;
+ bus->irq_opaque = irq_opaque;
bus->devfn_min = devfn_min;
bus->nirq = nirq;
bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
diff --git a/hw/pci.h b/hw/pci.h
index a2ec16a..10c9733 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -237,11 +237,11 @@ void pci_default_write_config(PCIDevice *d,
void pci_device_save(PCIDevice *s, QEMUFile *f);
int pci_device_load(PCIDevice *s, QEMUFile *f);
-typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
+typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
PCIBus *pci_register_bus(DeviceState *parent, const char *name,
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
- qemu_irq *pic, int devfn_min, int nirq);
+ void *irq_opaque, int devfn_min, int nirq);
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
const char *default_devaddr);
@@ -351,6 +351,6 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
/* sh_pci.c */
PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
- qemu_irq *pic, int devfn_min, int nirq);
+ void *pic, int devfn_min, int nirq);
#endif
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index d8aeeec..4739604 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -51,7 +51,7 @@ static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
return s->config_reg;
}
-static void piix3_set_irq(qemu_irq *pic, int irq_num, int level);
+static void piix3_set_irq(void *opaque, int irq_num, int level);
/* return the global irq number corresponding to a given device irq
pin. We could also use the bus number to have a more precise
@@ -231,9 +231,10 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic)
static PCIDevice *piix3_dev;
-static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
+static void piix3_set_irq(void *opaque, int irq_num, int level)
{
int i, pic_irq, pic_level;
+ qemu_irq *pic = opaque;
pci_irq_levels[irq_num] = level;
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index 98877cf..655fe86 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -304,8 +304,10 @@ static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
return slot - 1;
}
-static void ppc4xx_pci_set_irq(qemu_irq *pci_irqs, int irq_num, int level)
+static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
{
+ qemu_irq *pci_irqs = opaque;
+
DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
qemu_set_irq(pci_irqs[irq_num], level);
}
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 6328f73..64fccfd 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -253,8 +253,10 @@ static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
return ret;
}
-static void mpc85xx_pci_set_irq(qemu_irq *pic, int irq_num, int level)
+static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
{
+ qemu_irq *pic = opaque;
+
pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
qemu_set_irq(pic[irq_num], level);
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index 2a1d0f9..2d8a0fa 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -124,8 +124,10 @@ static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
return (irq_num + (pci_dev->devfn >> 3)) & 1;
}
-static void prep_set_irq(qemu_irq *pic, int irq_num, int level)
+static void prep_set_irq(void *opaque, int irq_num, int level)
{
+ qemu_irq *pic = opaque;
+
qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
}
diff --git a/hw/r2d.c b/hw/r2d.c
index ebcfbe7..24f1c64 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -182,8 +182,10 @@ static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
}
-static void r2d_pci_set_irq(qemu_irq *p, int n, int l)
+static void r2d_pci_set_irq(void *opaque, int n, int l)
{
+ qemu_irq *p = opaque;
+
qemu_set_irq(p[n], l);
}
diff --git a/hw/sh_pci.c b/hw/sh_pci.c
index 659935f..ea8635d 100644
--- a/hw/sh_pci.c
+++ b/hw/sh_pci.c
@@ -168,14 +168,14 @@ static MemOp sh_pci_iop = {
};
PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
- qemu_irq *pic, int devfn_min, int nirq)
+ void *opaque, int devfn_min, int nirq)
{
SHPCIC *p;
int mem, reg, iop;
p = qemu_mallocz(sizeof(SHPCIC));
p->bus = pci_register_bus(NULL, "pci",
- set_irq, map_irq, pic, devfn_min, nirq);
+ set_irq, map_irq, opaque, devfn_min, nirq);
p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
-1, NULL, NULL);
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index 908e046..5256541 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -141,8 +141,10 @@ static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
return (irq_num + (pci_dev->devfn >> 3)) & 3;
}
-static void pci_unin_set_irq(qemu_irq *pic, int irq_num, int level)
+static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
+ qemu_irq *pic = opaque;
+
qemu_set_irq(pic[irq_num + 8], level);
}
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index e36b10f..6767834 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -90,8 +90,10 @@ static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
return irq_num;
}
-static void pci_vpb_set_irq(qemu_irq *pic, int irq_num, int level)
+static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
{
+ qemu_irq *pic = opaque;
+
qemu_set_irq(pic[irq_num], level);
}
--
1.6.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH 07/13] Create PIIX3State instead of using PCIDevice for PIIX3
2009-08-27 23:15 [Qemu-devel] [PATCH 00/13] piix_pci cleanup Juan Quintela
` (5 preceding siblings ...)
2009-08-27 23:15 ` [Qemu-devel] [PATCH 06/13] We want the argument pass to set_irq to be opaque Juan Quintela
@ 2009-08-27 23:15 ` Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 08/13] Introduce PIIX3IrqState for piix3 irq's state Juan Quintela
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Juan Quintela @ 2009-08-27 23:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/piix_pci.c | 23 ++++++++++++++---------
1 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 4739604..29bd92c 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -33,6 +33,10 @@ typedef uint32_t pci_addr_t;
typedef PCIHostState I440FXState;
+typedef struct PIIX3State {
+ PCIDevice dev;
+} PIIX3State;
+
struct PCII440FXState {
PCIDevice dev;
target_phys_addr_t isa_page_descs[384 / 4];
@@ -229,7 +233,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic)
/* PIIX3 PCI to ISA bridge */
-static PCIDevice *piix3_dev;
+static PIIX3State *piix3_dev;
static void piix3_set_irq(void *opaque, int irq_num, int level)
{
@@ -240,13 +244,13 @@ static void piix3_set_irq(void *opaque, int irq_num, int level)
/* now we change the pic irq level according to the piix irq mappings */
/* XXX: optimize */
- pic_irq = piix3_dev->config[0x60 + irq_num];
+ pic_irq = piix3_dev->dev.config[0x60 + irq_num];
if (pic_irq < 16) {
/* The pic level is the logical OR of all the PCI irqs mapped
to it */
pic_level = 0;
for (i = 0; i < 4; i++) {
- if (pic_irq == piix3_dev->config[0x60 + i])
+ if (pic_irq == piix3_dev->dev.config[0x60 + i])
pic_level |= pci_irq_levels[i];
}
qemu_set_irq(pic[pic_irq], pic_level);
@@ -255,8 +259,8 @@ static void piix3_set_irq(void *opaque, int irq_num, int level)
static void piix3_reset(void *opaque)
{
- PCIDevice *d = opaque;
- uint8_t *pci_conf = d->config;
+ PIIX3State *d = opaque;
+ uint8_t *pci_conf = d->dev.config;
pci_conf[0x04] = 0x07; // master, memory and I/O
pci_conf[0x05] = 0x00;
@@ -307,14 +311,15 @@ static int piix_load(QEMUFile* f, void *opaque, int version_id)
return pci_device_load(d, f);
}
-static void piix3_initfn(PCIDevice *d)
+static void piix3_initfn(PCIDevice *dev)
{
+ PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
uint8_t *pci_conf;
- isa_bus_new(&d->qdev);
+ isa_bus_new(&d->dev.qdev);
register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);
- pci_conf = d->config;
+ pci_conf = d->dev.config;
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
@@ -345,7 +350,7 @@ static PCIDeviceInfo i440fx_info[] = {
},{
.qdev.name = "PIIX3",
.qdev.desc = "ISA bridge",
- .qdev.size = sizeof(PCIDevice),
+ .qdev.size = sizeof(PIIX3State),
.qdev.no_user = 1,
.init = piix3_initfn,
},{
--
1.6.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH 08/13] Introduce PIIX3IrqState for piix3 irq's state
2009-08-27 23:15 [Qemu-devel] [PATCH 00/13] piix_pci cleanup Juan Quintela
` (6 preceding siblings ...)
2009-08-27 23:15 ` [Qemu-devel] [PATCH 07/13] Create PIIX3State instead of using PCIDevice for PIIX3 Juan Quintela
@ 2009-08-27 23:15 ` Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 09/13] Fold piix3_init() intto i440fx_init Juan Quintela
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Juan Quintela @ 2009-08-27 23:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/piix_pci.c | 12 +++++++++---
1 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 29bd92c..0443a1d 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -37,6 +37,10 @@ typedef struct PIIX3State {
PCIDevice dev;
} PIIX3State;
+typedef struct PIIX3IrqState {
+ qemu_irq *pic;
+} PIIX3IrqState;
+
struct PCII440FXState {
PCIDevice dev;
target_phys_addr_t isa_page_descs[384 / 4];
@@ -217,11 +221,13 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic)
PCIBus *b;
PCIDevice *d;
I440FXState *s;
+ PIIX3IrqState *irq_state = qemu_malloc(sizeof(*irq_state));
+ irq_state->pic = pic;
dev = qdev_create(NULL, "i440FX-pcihost");
s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
b = pci_register_bus(&s->busdev.qdev, "pci.0",
- piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
+ piix3_set_irq, pci_slot_get_pirq, irq_state, 0, 4);
s->bus = b;
qdev_init(dev);
@@ -238,7 +244,7 @@ static PIIX3State *piix3_dev;
static void piix3_set_irq(void *opaque, int irq_num, int level)
{
int i, pic_irq, pic_level;
- qemu_irq *pic = opaque;
+ PIIX3IrqState *irq_state = opaque;
pci_irq_levels[irq_num] = level;
@@ -253,7 +259,7 @@ static void piix3_set_irq(void *opaque, int irq_num, int level)
if (pic_irq == piix3_dev->dev.config[0x60 + i])
pic_level |= pci_irq_levels[i];
}
- qemu_set_irq(pic[pic_irq], pic_level);
+ qemu_set_irq(irq_state->pic[pic_irq], pic_level);
}
}
--
1.6.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH 09/13] Fold piix3_init() intto i440fx_init
2009-08-27 23:15 [Qemu-devel] [PATCH 00/13] piix_pci cleanup Juan Quintela
` (7 preceding siblings ...)
2009-08-27 23:15 ` [Qemu-devel] [PATCH 08/13] Introduce PIIX3IrqState for piix3 irq's state Juan Quintela
@ 2009-08-27 23:15 ` Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 10/13] We can add piix3_dev now to PIIX3IrqState Juan Quintela
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Juan Quintela @ 2009-08-27 23:15 UTC (permalink / raw)
To: qemu-devel
i440fx_init will now work properly if we don't setup piix3
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/pc.c | 3 +--
hw/pc.h | 3 +--
hw/piix_pci.c | 18 ++++++------------
3 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/hw/pc.c b/hw/pc.c
index b240ae5..c05b759 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1279,8 +1279,7 @@ static void pc_init1(ram_addr_t ram_size,
ferr_irq = isa_irq[13];
if (pci_enabled) {
- pci_bus = i440fx_init(&i440fx_state, isa_irq);
- piix3_devfn = piix3_init(pci_bus, -1);
+ pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq);
} else {
pci_bus = NULL;
}
diff --git a/hw/pc.h b/hw/pc.h
index 3604c70..2234df5 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -120,9 +120,8 @@ int pcspk_audio_init(qemu_irq *pic);
struct PCII440FXState;
typedef struct PCII440FXState PCII440FXState;
-PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic);
+PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic);
void i440fx_set_smm(PCII440FXState *d, int val);
-int piix3_init(PCIBus *bus, int devfn);
void i440fx_init_memory_mappings(PCII440FXState *d);
/* piix4.c */
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 0443a1d..66aeb72 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -215,7 +215,9 @@ static void i440fx_initfn(PCIDevice *dev)
register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
}
-PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic)
+static PIIX3State *piix3_dev;
+
+PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
{
DeviceState *dev;
PCIBus *b;
@@ -234,13 +236,14 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic)
d = pci_create_simple(b, 0, "i440FX");
*pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
+ piix3_dev = DO_UPCAST(PIIX3State, dev, pci_create_simple(b, -1, "PIIX3"));
+ *piix3_devfn = piix3_dev->dev.devfn;
+
return b;
}
/* PIIX3 PCI to ISA bridge */
-static PIIX3State *piix3_dev;
-
static void piix3_set_irq(void *opaque, int irq_num, int level)
{
int i, pic_irq, pic_level;
@@ -332,19 +335,10 @@ static void piix3_initfn(PCIDevice *dev)
pci_conf[PCI_HEADER_TYPE] =
PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
- piix3_dev = d;
piix3_reset(d);
qemu_register_reset(piix3_reset, d);
}
-int piix3_init(PCIBus *bus, int devfn)
-{
- PCIDevice *d;
-
- d = pci_create_simple(bus, devfn, "PIIX3");
- return d->devfn;
-}
-
static PCIDeviceInfo i440fx_info[] = {
{
.qdev.name = "i440FX",
--
1.6.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH 10/13] We can add piix3_dev now to PIIX3IrqState
2009-08-27 23:15 [Qemu-devel] [PATCH 00/13] piix_pci cleanup Juan Quintela
` (8 preceding siblings ...)
2009-08-27 23:15 ` [Qemu-devel] [PATCH 09/13] Fold piix3_init() intto i440fx_init Juan Quintela
@ 2009-08-27 23:15 ` Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 11/13] Save irq_state into PCII440FXState Juan Quintela
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Juan Quintela @ 2009-08-27 23:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/piix_pci.c | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 66aeb72..d77c6e6 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -38,6 +38,7 @@ typedef struct PIIX3State {
} PIIX3State;
typedef struct PIIX3IrqState {
+ PIIX3State *piix3;
qemu_irq *pic;
} PIIX3IrqState;
@@ -215,8 +216,6 @@ static void i440fx_initfn(PCIDevice *dev)
register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
}
-static PIIX3State *piix3_dev;
-
PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
{
DeviceState *dev;
@@ -236,8 +235,9 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *
d = pci_create_simple(b, 0, "i440FX");
*pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
- piix3_dev = DO_UPCAST(PIIX3State, dev, pci_create_simple(b, -1, "PIIX3"));
- *piix3_devfn = piix3_dev->dev.devfn;
+ irq_state->piix3 = DO_UPCAST(PIIX3State, dev,
+ pci_create_simple(b, -1, "PIIX3"));
+ *piix3_devfn = irq_state->piix3->dev.devfn;
return b;
}
@@ -253,13 +253,13 @@ static void piix3_set_irq(void *opaque, int irq_num, int level)
/* now we change the pic irq level according to the piix irq mappings */
/* XXX: optimize */
- pic_irq = piix3_dev->dev.config[0x60 + irq_num];
+ pic_irq = irq_state->piix3->dev.config[0x60 + irq_num];
if (pic_irq < 16) {
/* The pic level is the logical OR of all the PCI irqs mapped
to it */
pic_level = 0;
for (i = 0; i < 4; i++) {
- if (pic_irq == piix3_dev->dev.config[0x60 + i])
+ if (pic_irq == irq_state->piix3->dev.config[0x60 + i])
pic_level |= pci_irq_levels[i];
}
qemu_set_irq(irq_state->pic[pic_irq], pic_level);
--
1.6.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH 11/13] Save irq_state into PCII440FXState
2009-08-27 23:15 [Qemu-devel] [PATCH 00/13] piix_pci cleanup Juan Quintela
` (9 preceding siblings ...)
2009-08-27 23:15 ` [Qemu-devel] [PATCH 10/13] We can add piix3_dev now to PIIX3IrqState Juan Quintela
@ 2009-08-27 23:15 ` Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 12/13] pci_irq_levels[] belong to PIIX3State Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 13/13] Update SaveVM versions Juan Quintela
12 siblings, 0 replies; 14+ messages in thread
From: Juan Quintela @ 2009-08-27 23:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/piix_pci.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index d77c6e6..8e01a52 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -46,6 +46,7 @@ struct PCII440FXState {
PCIDevice dev;
target_phys_addr_t isa_page_descs[384 / 4];
uint8_t smm_enabled;
+ PIIX3IrqState *irq_state;
};
static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
@@ -234,6 +235,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *
d = pci_create_simple(b, 0, "i440FX");
*pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
+ (*pi440fx_state)->irq_state = irq_state;
irq_state->piix3 = DO_UPCAST(PIIX3State, dev,
pci_create_simple(b, -1, "PIIX3"));
--
1.6.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH 12/13] pci_irq_levels[] belong to PIIX3State
2009-08-27 23:15 [Qemu-devel] [PATCH 00/13] piix_pci cleanup Juan Quintela
` (10 preceding siblings ...)
2009-08-27 23:15 ` [Qemu-devel] [PATCH 11/13] Save irq_state into PCII440FXState Juan Quintela
@ 2009-08-27 23:15 ` Juan Quintela
2009-08-27 23:15 ` [Qemu-devel] [PATCH 13/13] Update SaveVM versions Juan Quintela
12 siblings, 0 replies; 14+ messages in thread
From: Juan Quintela @ 2009-08-27 23:15 UTC (permalink / raw)
To: qemu-devel
With previous cleanups, now it is possible to put it where it belongs
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/piix_pci.c | 13 ++++++-------
1 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 8e01a52..580c987 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -35,6 +35,7 @@ typedef PCIHostState I440FXState;
typedef struct PIIX3State {
PCIDevice dev;
+ int pci_irq_levels[4];
} PIIX3State;
typedef struct PIIX3IrqState {
@@ -73,8 +74,6 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
return (irq_num + slot_addend) & 3;
}
-static int pci_irq_levels[4];
-
static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
{
uint32_t addr;
@@ -164,7 +163,7 @@ static void i440fx_save(QEMUFile* f, void *opaque)
qemu_put_8s(f, &d->smm_enabled);
for (i = 0; i < 4; i++)
- qemu_put_be32(f, pci_irq_levels[i]);
+ qemu_put_be32(f, d->irq_state->piix3->pci_irq_levels[i]);
}
static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
@@ -182,7 +181,7 @@ static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
if (version_id >= 2)
for (i = 0; i < 4; i++)
- pci_irq_levels[i] = qemu_get_be32(f);
+ d->irq_state->piix3->pci_irq_levels[i] = qemu_get_be32(f);
return 0;
}
@@ -251,7 +250,7 @@ static void piix3_set_irq(void *opaque, int irq_num, int level)
int i, pic_irq, pic_level;
PIIX3IrqState *irq_state = opaque;
- pci_irq_levels[irq_num] = level;
+ irq_state->piix3->pci_irq_levels[irq_num] = level;
/* now we change the pic irq level according to the piix irq mappings */
/* XXX: optimize */
@@ -262,7 +261,7 @@ static void piix3_set_irq(void *opaque, int irq_num, int level)
pic_level = 0;
for (i = 0; i < 4; i++) {
if (pic_irq == irq_state->piix3->dev.config[0x60 + i])
- pic_level |= pci_irq_levels[i];
+ pic_level |= irq_state->piix3->pci_irq_levels[i];
}
qemu_set_irq(irq_state->pic[pic_irq], pic_level);
}
@@ -305,7 +304,7 @@ static void piix3_reset(void *opaque)
pci_conf[0xac] = 0x00;
pci_conf[0xae] = 0x00;
- memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
+ memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
}
static void piix_save(QEMUFile* f, void *opaque)
--
1.6.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH 13/13] Update SaveVM versions
2009-08-27 23:15 [Qemu-devel] [PATCH 00/13] piix_pci cleanup Juan Quintela
` (11 preceding siblings ...)
2009-08-27 23:15 ` [Qemu-devel] [PATCH 12/13] pci_irq_levels[] belong to PIIX3State Juan Quintela
@ 2009-08-27 23:15 ` Juan Quintela
12 siblings, 0 replies; 14+ messages in thread
From: Juan Quintela @ 2009-08-27 23:15 UTC (permalink / raw)
To: qemu-devel
Now that we have all fields belonging to a PCIDevice, save each field
on the device that it belongs. This means moving pci_irq_levels
from PCII440FXState to PIIX3State.
Old formats are loaded, but we only save on the new saner format.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/piix_pci.c | 40 +++++++++++++++++++++++++---------------
1 files changed, 25 insertions(+), 15 deletions(-)
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 580c987..49852e1 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -157,13 +157,9 @@ static void i440fx_write_config(PCIDevice *dev,
static void i440fx_save(QEMUFile* f, void *opaque)
{
PCII440FXState *d = opaque;
- int i;
pci_device_save(&d->dev, f);
qemu_put_8s(f, &d->smm_enabled);
-
- for (i = 0; i < 4; i++)
- qemu_put_be32(f, d->irq_state->piix3->pci_irq_levels[i]);
}
static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
@@ -171,7 +167,7 @@ static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
PCII440FXState *d = opaque;
int ret, i;
- if (version_id > 2)
+ if (version_id > 3)
return -EINVAL;
ret = pci_device_load(&d->dev, f);
if (ret < 0)
@@ -179,7 +175,7 @@ static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
i440fx_update_memory_mappings(d);
qemu_get_8s(f, &d->smm_enabled);
- if (version_id >= 2)
+ if (version_id == 2)
for (i = 0; i < 4; i++)
d->irq_state->piix3->pci_irq_levels[i] = qemu_get_be32(f);
@@ -213,7 +209,7 @@ static void i440fx_initfn(PCIDevice *dev)
d->dev.config[0x72] = 0x02; /* SMRAM */
- register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
+ register_savevm("I440FX", 0, 3, i440fx_save, i440fx_load, d);
}
PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
@@ -307,18 +303,32 @@ static void piix3_reset(void *opaque)
memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
}
-static void piix_save(QEMUFile* f, void *opaque)
+static void piix3_save(QEMUFile* f, void *opaque)
{
- PCIDevice *d = opaque;
- pci_device_save(d, f);
+ PIIX3State *d = opaque;
+ int i;
+
+ pci_device_save(&d->dev, f);
+
+ for (i = 0; i < 4; i++)
+ qemu_put_be32(f, d->pci_irq_levels[i]);
}
-static int piix_load(QEMUFile* f, void *opaque, int version_id)
+static int piix3_load(QEMUFile* f, void *opaque, int version_id)
{
- PCIDevice *d = opaque;
- if (version_id != 2)
+ PIIX3State *d = opaque;
+ int i, ret;
+
+ if (version_id > 3 || version_id < 2)
return -EINVAL;
- return pci_device_load(d, f);
+ ret = pci_device_load(&d->dev, f);
+ if (ret < 0)
+ return ret;
+ if (version_id >= 3) {
+ for (i = 0; i < 4; i++)
+ d->pci_irq_levels[i] = qemu_get_be32(f);
+ }
+ return 0;
}
static void piix3_initfn(PCIDevice *dev)
@@ -327,7 +337,7 @@ static void piix3_initfn(PCIDevice *dev)
uint8_t *pci_conf;
isa_bus_new(&d->dev.qdev);
- register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);
+ register_savevm("PIIX3", 0, 3, piix3_save, piix3_load, d);
pci_conf = d->dev.config;
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
--
1.6.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread